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path: root/src/mesa/drivers/dri/i965/brw_wm_glsl.c
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2009-08-12i965: Allocate destination registers for GLSL TEX instructions contiguously.Eric Anholt
This matches brw_wm_pass*.c behavior, and fixes the norsetto shadow demo. Bug #19489
2009-08-12i965: drop dead scalar handling in GLSL.Eric Anholt
2009-08-12i965: Drop GLSL ABS code, which is translated away in brw_wm_fp.Eric Anholt
2009-08-12i965: Drop code for emitting OPCODE_SUB, since brw_wm_fp.c makes it an ADD.Eric Anholt
2009-08-12i965: Handle scalar result swizzling in shared GLSL/non-GLSL code.Eric Anholt
This is preparation for merging of brw_wm_glsl.c and brw_wm_emit.c, and glsl.c doesn't swizzle channel results around.
2009-08-12i965: Flag ARL-using programs as requiring brw_wm_glsl.cEric Anholt
This doesn't fix the glean testcase, but I guess it provides hope.
2009-08-04i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out, and running intel-gen4disasm on it.
2009-07-31Rename TGSI LOOP instruction to better match theri usage.Michal Krol
The LOOP/ENDLOOP pair is renamed to BGNFOR/ENDFOR as its behaviour is similar to a C language for-loop. The BGNLOOP2/ENDLOOP2 pair is renamed to BGNLOOP/ENDLOOP as now there is no name collision.
2009-07-15i965: the offset of any branch/jump instruction is in unit of 64bits on IGDNGXiang, Haihao
2009-07-13i965: add support for new chipsetsXiang, Haihao
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-06-26i965: fix fetching constants from constant buffer in glsl pathRoland Scheidegger
the driver used to overwrite grf0 then use implicit move by send instruction to move contents of grf0 to mrf1. However, we must not overwrite grf0 since it's still used later for fb write. Instead, do the move directly do mrf1 (we could use implicit move from another grf reg to mrf1 but since we need a mov to encode the data anyway it doesn't seem to make sense). I think the dp_READ/WRITE_16 functions may suffer from the same issue. While here also remove unnecessary msg_reg_nr parameter from the dataport functions since always message register 1 is used.
2009-06-19i965: asst clean-ups, var renaming in brw_wm_emit_glsl()Brian Paul
2009-06-16i965: handle OPCODE_SWZ in the glsl pathRoland Scheidegger
glsl compiler will not generate OPCODE_SWZ, and as a first step it would be translated away to a MOV anyway (why?), but later internally this opcode is generated (for EXT_texture_swizzling).
2009-06-02i965: Support OPCODE_TRUNC in the brw_wm_fp.c code.Eric Anholt
This gets two more glean glsl1 tests using the non-GLSL path.
2009-05-14i965: Fix register allocation of GLSL fp inputs.Eric Anholt
Before, if the VP output something that is in the attributes coming into the WM but which isn't used by the WM, then WM would end up reading subsequent varyings from the wrong places. This was visible with a GLSL demo using gl_PointSize in the VS and a varying in the WM, as point size is in the VUE but not used by the WM. There is now a regression test in piglit, glsl-unused-varying.
2009-05-12i965: enable additional code in emit_fb_write()Brian Paul
Not 100% sure this is right, but the invalid assertion is fixed...
2009-05-11i965: handle extended swizzle terms (0,1) in get_src_reg()Brian Paul
Fixes failed assertion in progs/glsl/twoside.c (but still wrong rendering).
2009-05-08i965: don't use GRF regs 126,127 for WM programsBrian Paul
They seem to be used for something else and using them for shader temps seems to lead to GPU lock-ups. Call _mesa_warning() when we run out of temps. Also, clean up some debug code.
2009-05-06i965: Remove bad constant buffer constant-reg-already-loaded optimization.Eric Anholt
Thanks to branching, the state of c->current_const[i].index at the point of emitting constant loads for this instruction may not match the actual constant currently loaded in the reg at runtime. Fixes a regression in my GLSL program for idr's class since b58b3a786aa38dcc9d72144c2cc691151e46e3d5.
2009-05-01Merge branch 'const-buffer-changes'Brian Paul
Conflicts: src/mesa/drivers/dri/i965/brw_curbe.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/i965/brw_wm_glsl.c
2009-04-27i965: only upload constant buffer data when we actually need the const bufferBrian Paul
Make the use_const_buffer field per-program and only call the code which updates the constant buffer's data if the flag is set. This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052 (cherry picked from master, commit dc9705d12d162ba6d087eb762e315de9f97bc456)
2009-04-27i965: only upload constant buffer data when we actually need the const bufferBrian Paul
Make the use_const_buffer field per-program and only call the code which updates the constant buffer's data if the flag is set. This should undo the perf regression from 20f3497e4b6756e330f7b3f54e8acaa1d6c92052
2009-04-24i965: rework GLSL/WM register allocationBrian Paul
Use a bitvector of used/free flags. If we run out of temps, examine the live intervals of the temp regs in the program and free those which are no longer alive. Also, enable the new WM const buffer code.
2009-04-21i965: const correctnessBrian Paul
2009-04-16Merge branch 'register-negate'Brian Paul
2009-04-16i965: disable using immediate values for MOV instructionsBrian Paul
For some reason, MOV instructions using immediate src values don't seem to work reliably on the GLSL path. Disable them for now (falling back to const buffer reads). This fixes a bunch of glean glsl1 failures.
2009-04-16i965: minor debug output changesBrian Paul
2009-04-14mesa: merge the prog_src_register::NegateBase and NegateAbs fieldsBrian Paul
There's really no need for two negation fields. This came from the GL_NV_fragment_program extension. The new, unified Negate bitfield applies after the absolute value step.
2009-04-09i965: new SURF_INDEX_ macrosBrian Paul
Used to map drawables, textures and constant buffers to surface binding table indexes.
2009-04-08i965: clean-ups, debug code in brw_wm_glsl.cBrian Paul
2009-04-08i965: init current_const[i].index = -1Brian Paul
2009-04-08i965: move the fetch_constants() call before setting conditional mod stateBrian Paul
Before, the instruction's CondUpdate field was mistakenly effecting the constant-fetch operation. Fixes progs/glsl/bump.c demo. But there are some other issues related to condition flags and IF/ELSE that need investigation...
2009-04-03i965: more const buffer debug codeBrian Paul
2009-04-03i965: another checkpoint commit of new constant buffer supportBrian Paul
Everything is in place now for using a true constant buffer for GLSL fragment shaders. Still some bugs to find though.
2009-04-03i965: change args to get_src_reg() to prep for new constant buffer supportBrian Paul
2009-04-03i965: check-point commit of new constant buffer supportBrian Paul
Currently, shader constants are stored in the GRF (loaded from the CURBE prior to shader execution). This severly limits the number of constants and temps that we can support. This new code will support (practically) unlimited size constant buffers and free up registers in the GRF. We allocate a new buffer object for the constants and read them with "Read" messages/instructions. When only a small number of constants are used, we can still use the old method. The code works for fragment shaders only (and is actually disabled) for now. Need to do the same thing for vertex shaders and need to add the necessary code-gen to fetch the constants which are referenced by the shader instructions.
2009-04-03i965: do negation and Abs in get_src_reg_imm()Brian Paul
Fixes regression seen with progs/glsl/bump.c
2009-04-03i965: comments for sampling codeBrian Paul
2009-04-03i965: add support for float literal instruction operandsBrian Paul
Call the get_src_reg_imm() function when it's permissible to generate a literal value src register.
2009-04-03i965: remove 'nr' param from get_src/dst_reg() functionsBrian Paul
The value was always 1.
2009-04-03i965: fix comment typoBrian Paul
2009-03-23i965: Fix glFrontFacing in twoside GLSL demo.Eric Anholt
This also cuts instructions by just using the existing bit in the payload rather than computing it from the determinant in the SF unit and passing it as a varying down to the WM. Something still goes wrong with getting the backface color right, but a simpler shader appears to get the right result.
2009-03-13i965: move declarations before codeBrian Paul
2009-03-11i965: fix lock-ups when GLSL program wrote to gl_FragDepthBrian Paul
It seems the code that set up the FB_WRITE message was incomplete in this case. The number of payload registers was wrong and that caused a hang. It would be good to have a second set of eyes take a look at this...
2009-03-10i965: more code clean-ups, commentsBrian Paul
2009-03-10i965: minor code clean-ups, commentsBrian Paul
2009-03-06i965: check if we run out of GRF/temp registersBrian Paul
Before this change we would up emitting instructions with invalid register numbers. This typically (but not always) hung the GPU. For now, just prevent emitting bad instructions to avoid hangs. Still need to do some kind of proper error recovery.
2009-03-06i965: comments and minor clean-upsBrian Paul
2009-03-05i965: comments and formatting fixesBrian Paul
2009-03-05i965: fix emit_math1() function used for scalar instructionsBrian Paul
Instructions such as RCP, RSQ, LOG must smear the result of the function across the dest register's X, Y, Z and W channels (subject to write masking). Before this change, only the X component was getting written. Among other things, this fixes cube map texture sampling in GLSL shaders (since cube lookups involve normalizing the texcoord).