summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri/i965/brw_wm_glsl.c
AgeCommit message (Collapse)Author
2009-03-06i965: check if we run out of GRF/temp registersBrian Paul
Before this change we would up emitting instructions with invalid register numbers. This typically (but not always) hung the GPU. For now, just prevent emitting bad instructions to avoid hangs. Still need to do some kind of proper error recovery.
2009-03-06i965: comments and minor clean-upsBrian Paul
2009-03-05i965: comments and formatting fixesBrian Paul
2009-03-05i965: fix emit_math1() function used for scalar instructionsBrian Paul
Instructions such as RCP, RSQ, LOG must smear the result of the function across the dest register's X, Y, Z and W channels (subject to write masking). Before this change, only the X component was getting written. Among other things, this fixes cube map texture sampling in GLSL shaders (since cube lookups involve normalizing the texcoord).
2009-02-26mesa: replace old prog_instruction::Sampler field with Aux fieldBrian Paul
The i965 driver needs an extra instruction field for color output information. It was using the Sampler field for this. Use the Aux field instead. This will probaby be revisited at some point...
2009-02-20i965: additional debug outputBrian Paul
2009-02-13i965: rewrite the code for handling shader subroutine callsBrian Paul
Previously, the prog_instruction::Data field was used to map original Mesa instructions to brw instructions in order to resolve subroutine calls. This was a rather tangled mess. Plus it's an obstacle to implementing dynamic allocation/growing of the instruction buffer (it's still a fixed size). Mesa's GLSL compiler emits a label for each subroutine and CAL instruction. Now we use those labels to patch the subroutine calls after code generation has been done. We just keep a list of all CAL instructions that needs patching and a list of all subroutine labels. It's a simple matter to resolve them. This also consolidates some redundant post-emit code between brw_vs_emit.c and brw_wm_glsl.c and removes some loops that cleared the prog_instruction::Data fields at the end. Plus, a bunch of new comments.
2009-02-13i965: updated commentsBrian Paul
2009-02-13i965: more reformatting/clean-upBrian Paul
2009-02-13i965: s/__inline/INLINE/Brian Paul
2009-02-13i965: formatting and indentation fixesBrian Paul
2009-01-14i965: comment for emit_kil()Brian Paul
2009-01-14i965: fix indentationBrian Paul
2009-01-07i965: Fix GLSL FS DPH to return the right value instead of src0.w * src1.w.Eric Anholt
2009-01-05i965: implement OPCODE_TRUNC (round toward zero) on vertex path.Brian Paul
Also, fix some RNDD vs. RNDZ confusion elsewhere.
2008-12-13i965: Finish OPCODE_NOISEn instructions.Gary Wong
Added missing OPCODE_NOISE4, and use BRW_REGISTER_TYPE_D (instead of _UD) in the initial RNDD instructions (which avoids saturating negative inputs to 0).
2008-11-06mesa: rename OPCODE_INT -> OPCODE_TRUNCBrian Paul
Trunc is a more accurate description; there's no type conversion involved.
2008-11-05i965: Implement missing OPCODE_NOISE3 instruction in fragment shaders.Gary Wong
OPCODE_NOISE4 coming later.
2008-10-31i965: implement the missing OPCODE_NOISE1 and OPCODE_NOISE2 instructions.Gary Wong
(Only in fragment shaders, so far. Support for NOISE3 and NOISE4 to come.)
2008-10-28i965: Allocate temporaries contiguously with other regs in fragment shaders.Gary Wong
This is required for threads to be spawned with correctly sized GRF register blocks.
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul
Makefile.template
2008-08-29i965: Push/pop instruction state. partial fix for #16882Xiang, Haihao
2008-08-05i965: Use program->SamplerUnits[] to get the appropriate texture unit.Xiang, Haihao
inst->TexSrcUnit is used as an index into program->SamplerUnits[] since the commit ade508312c701ce89d3c2cd717994dbbabb4f207, and program->SamplerUnits is a sampler-to-texture-unit mapping.
2008-06-10i965: apply commit 6c1a98e97affb2163e776551eb3a9e669ff99bbf to glslXiang, Haihao
2008-03-17 [i965] fix wpos height 1 pixel higherZou Nan hai
2008-03-13 [i965] multiple rendering target supportZou Nan hai
2008-02-28[965] Bug #9151: make fragment.position return window coords not screen coords.Eric Anholt
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2007-12-14[intel] warnings cleanupEric Anholt
2007-11-30i965: if source depth to render target is set,Xiang, Haihao
it should be handled in fb_write.
2007-10-09 fix for prev commitZou Nan hai
2007-10-09 INT supportZou Nan hai
2007-10-09 shadow sampler fix.Zou Nan hai
1. spec requite result (0, 0, 0, 1) instead of (0, 0, 0, 0) 2. support shadow sampler in simd8
2007-09-30 fragment shader function call fix, gl_FragCoord fixZou Nan hai
2007-09-29 support continue, fix conditionalZou Nan hai
2007-09-28 fixZou Nan hai
2007-09-28support nested function call in pixel shaderZou Nan hai
2007-09-27 handle INT op, still require high level handle of integer to be correctZou Nan hai
2007-09-18fix double free in 965-glsl branchZou Nan hai
2007-07-24 DDX DDY support, not very accurateZou Nan hai
2007-07-17 Fix SOP in fragment shader, brick is ok now.Zou Nan hai
2007-07-05 support "discard";Zou Nan hai
2007-06-21 support branch and loop in pixel shaderZou Nan hai
most of the sample working with some small modification