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path: root/src/mesa/drivers/dri/i965/brw_wm_pass2.c
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2010-12-06i965: Fix gen6 interpolation setup for 16-wide.Eric Anholt
In the SF and brw_fs.cpp fixes to set up interpolation sanely on gen6, the setup for 16-wide interpolation was left behind. This brings relative sanity to that path too.
2010-12-06i965: Move payload reg setup to compile, not lookup time.Eric Anholt
Payload reg setup on gen6 depends more on the dispatch width as well as the uses_depth, computes_depth, and other flags. That's something we want to decide at compile time, not at cache lookup. As a bonus, the fragment shader program cache lookup should be cheaper now that there's less to compute for the hash key.
2010-11-03intel: Annotate debug printout checks with unlikely().Eric Anholt
This provides the optimizer with hints about code hotness, which we're quite certain about for debug printouts (or, rather, while we developers often hit the checks for debug printouts, we don't care about performance while doing so).
2010-08-30i965: Align the number of payload regs to 2 again in 16-wide mode.Eric Anholt
Fixes a regression in point-line-no-cull and glean/paths tests since 501c9dc62774a73c080d500a1eab773b0da9577e.
2010-08-20i965: Rename nr_depth_regs to nr_payload_regs.Eric Anholt
Only 8 out of the up to 13 regs are for source/dest depth, so the name wasn't particularly appropriate. Note that this doesn't count the constant or URB payload regs. Also, don't pre-divide by 2, so it's actually a number of registers.
2009-11-17Merge branch 'outputswritten64'Ian Romanick
Add a GLbitfield64 type and several macros to operate on 64-bit fields. The OutputsWritten field of gl_program is changed to use that type. This results in a fair amount of fallout in drivers that use programs. No changes are strictly necessary at this point as all bits used are below the 32-bit boundary. Fairly soon several bits will be added for clip distances written by a vertex shader. This will cause several bits used for varyings to be pushed above the 32-bit boundary. This will affect any drivers that support GLSL. At this point, only the i965 driver has been modified to support this eventuality. I did this as a "squash" merge. There were several places through the outputswritten64 branch where things were broken. I foresee this causing difficulties later for bisecting. The history is still available in the branch. Conflicts: src/mesa/drivers/dri/i965/brw_wm.h
2009-05-14i965: Fix varying payload reg assignment for the non-GLSL-instructions path.Eric Anholt
I don't have a testcase for this, but it seems clearly wrong.
2009-05-14i965: Fix register allocation of GLSL fp inputs.Eric Anholt
Before, if the VP output something that is in the attributes coming into the WM but which isn't used by the WM, then WM would end up reading subsequent varyings from the wrong places. This was visible with a GLSL demo using gl_PointSize in the VS and a varying in the WM, as point size is in the VUE but not used by the WM. There is now a regression test in piglit, glsl-unused-varying.
2009-01-22i965: whitespace changes and reformattingBrian Paul
2008-02-19 fix compile for previous commitZou Nan hai
2008-02-19[i965] fix broken glsl texdemo1Zou Nan hai
2008-02-14i965: use setup attributes as inputs when allocating registersXiang, Haihao
for WM payload. fix #10767
2007-06-21 support branch and loop in pixel shaderZou Nan hai
most of the sample working with some small modification
2007-02-23Update DRI drivers for new glsl compiler.Brian
Mostly: - update #includes - update STATE_* token code
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.