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path: root/src/mesa/drivers/dri/i965/brw_wm_state.c
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2007-10-26Merge branch '965-glsl'Zou Nan hai
Conflicts: src/mesa/drivers/dri/i965/brw_sf.h src/mesa/drivers/dri/i965/intel_context.c
2007-10-04[965] Replace various alignment code with a shared ALIGN() macro.Eric Anholt
In the process, fix some alignment issues: - Scratch space allocation was aligned into units of 1KB, while the allocation wanted units of bytes, so we never allocated enough space for scratch. - GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
2007-09-27Revert "WIP 965 conversion to dri_bufmgr."Eric Anholt
This reverts commit b2f1aa2389473ed09170713301b042661d70a48e. Somehow I ended up with my branch's save-this-while-I-work-on-master commit actually on master.
2007-09-27WIP 965 conversion to dri_bufmgr.Eric Anholt
2007-08-29i965: samplers group in fours in WM_STATE. fix bug#9415Xiang, Haihao
2007-06-21 support branch and loop in pixel shaderZou Nan hai
most of the sample working with some small modification
2007-01-06Various warning fixes for i965 driver.Keith Packard
vertex/fragment programs provided as const. bmSetFenceLock should return bmSetFence value.
2007-01-06i965: ARB_occlusion_query supportWang Zhenyu
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-09-07Use lower alignments where possible. Also pad out allocated blocks toKeith Whitwell
a multiple of alignment to avoid accumulating unusable free blocks.
2006-09-07Make sure bmBufferOffset is called for all active buffers every timeKeith Whitwell
we render. Currenly requires that some state be re-examined after every LOCK_HARDWARE().
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.