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path: root/src/mesa/drivers/dri/i965/intel_blit.c
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2007-10-30More vblank cleanups.Michel Dänzer
* Fix crash at context creation in most drivers supporting vblank. * Don't pass vblank sequence or flags to functions that get passed the drawable private already. * Attempt to initialize vblank related drawable private fields just once per drawable. May need more work in some drivers.
2007-10-29Refactor and fix core vblank supportJesse Barnes
Consolidate support for synchronizing to and retrieving vblank counters. Also fix the core vblank code to return monotonic MSC counters, which are required by some GLX extensions. Adding support for multiple pipes to a low level driver is fairly easy, the Intel 965 driver provides simple example code (see intel_buffers.c:intelWindowMoved()). The new code bumps the media stream counter extension version to 2 and adds a new getDrawableMSC callback. This callback takes a drawablePrivate pointer, which is used to calculate the MSC value seen by clients based on the actual vblank counter(s) returned from the kernel. The new drawable private fields are as follows: - vblSeq - used for tracking vblank counts for buffer swapping - vblFlags - flags (e.g. current pipe), updated by low level driver - msc_base - MSC counter from the last time the current pipe changed - vblank_base - kernel DRM vblank counter from the last time the pipe changed Using the above variables, the core vblank code (in vblank.c) can calculate a monotonic MSC value. The low level DRI drivers are responsible for updating the current pipe (by setting VBLANK_FLAG_SECONDARY for example in vblFlags) along with msc_base and vblank_base whenever the pipe associated with a given drawable changes (again, see intelWindowMoved for an example of this). Drivers should fill in the GetDrawableMSC DriverAPIRec field to point to driDrawableGetMSC32 and add code for pipe switching as outlined above to fully support the new scheme.
2007-10-04[965] Replace various alignment code with a shared ALIGN() macro.Eric Anholt
In the process, fix some alignment issues: - Scratch space allocation was aligned into units of 1KB, while the allocation wanted units of bytes, so we never allocated enough space for scratch. - GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
2007-10-04Replace bmBufferOffset usage in batchbuffer setup with OUT_RELOC.Eric Anholt
This is in preparation for 965 TTM.
2007-10-04Replace duplicated intel_reg.h with a shared header.Eric Anholt
2007-10-04Replace some structure-based batch preparation with plain OUT_BATCH.Eric Anholt
OUT_BATCH is far more amenable to the upcoming relocations being done for TTM support.
2007-09-27Revert "WIP 965 conversion to dri_bufmgr."Eric Anholt
This reverts commit b2f1aa2389473ed09170713301b042661d70a48e. Somehow I ended up with my branch's save-this-while-I-work-on-master commit actually on master.
2007-09-27WIP 965 conversion to dri_bufmgr.Eric Anholt
2007-07-04fix LogicOp/bitmap problem, bug 11133Eric Anholt
2007-01-06i965: xdemos/glxthreads get: Assertion `block->fenced' failed (9201)Zou Nan hai
Signed-off-by: Keith Packard <keithp@neko.keithp.com>
2006-11-21Gary Wong's patches for CopyPixels Logiop (enable) and BlendKeith Whitwell
(disallow). Slightly cleaned to disallow on all blend states for code consiseness and turn a table lookup into a function to match other code in the driver.
2006-11-01Remove x/y/width/height parameters from Clear functions.Brian Paul
2006-10-05Accelerate glBitmap with a color expand blit. Nice speedup for demosKeith Whitwell
like 'fire' that display a help message or fps number this way.
2006-09-22Explicit test for +ve pitches in intelEmitCopyBlit()Keith Whitwell
2006-09-20Add a comment about the interactions of negative pitches, overlappingKeith Whitwell
blits and the different ways of specifying a blit on this hardware.
2006-09-20Broadwater seems to prefer this style of blitting.Keith Whitwell
2006-08-09Add Intel i965G/Q DRI driver.Eric Anholt
This driver comes from Tungsten Graphics, with a few further modifications by Intel.