summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri/i965/intel_context.c
AgeCommit message (Collapse)Author
2008-02-22intel: Merge intel_context.c from i915 and i965.Kristian Høgsberg
2008-02-22Merge {i915,i965}/intel_context.h as intel/intel_context.hKristian Høgsberg
2008-02-22Use drm_i915_sarea instead of drmI830Sarea and remove i830_common.hAlan Hourihane
2008-02-13[965] Fix ARB_occlusion_query from intel_screen.c merge.Eric Anholt
It wasn't being initialized at screen setup, so we were getting stub entrypoints even though it was exposed as enabled. Fixes arbocclude mesa demo.
2008-02-03i965: fix potential NULL pointer dereference. The third regionXiang, Haihao
isn't created at all for 965
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2008-01-17[intel] Make the no_rast option be standard driconf instead of INTEL_NO_RAST.Eric Anholt
2008-01-10[intel] Add more cliprect modes to cover other meanings for batch emits.Eric Anholt
The previous change gave us only two modes, one which looped over the batch per cliprect (3d drawing) and one that didn't (state updeast). However, we really want 4: - Batch doesn't care about cliprects (state updates) - Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing) - Batch needs to be executed just once (region fills, copies, etc.) - Batch already includes cliprect handling, and must be flushed by unlock time (copybuffers, clears). All callers should now be fixed to use one of these states for any batchbuffer emits. Thanks to Keith Whitwell for pointing out the failure.
2008-01-10i965: fix segfault caused by commit e131c46b20241737ceba4856dbe01dcca6dd2c03.Xiang, Haihao
2008-01-09[intel] Rename lost_hardware vtbl entry to new_batch.Eric Anholt
Both drivers have ended up relying on lost_hardware being called after each batch buffer, so update the name. This removes one of the calls on 965 whic h was outside of the batchbuffer handling code and just duplicating what had already happened through batchbuffer handling.
2008-01-09[intel] Remove the dead intel->need_flush member.Eric Anholt
2007-12-21[965] Fix and enable separate stencil.Eric Anholt
Note that this does not enable GL_EXT_stencil_two_side, because Mesa's computed _TestTwoSide ends up respecting only STENCIL_TEST_TWO_SIDE_EXT (defaults to GL_FALSE), even if the application uses only GL 2.0 / ATI entrypoints.
2007-12-20[965] Enable EXT_framebuffer_object.Eric Anholt
To do so, merge the remainnig necessary code from the buffers, blit, span, and screen code to shared, and replace it with those.
2007-12-20[965] Actually enable SGIS_generate_mipmap.Eric Anholt
2007-12-17[965] Replace our own depth constants in intel context with GL context ones.Eric Anholt
2007-12-16[965] Enable ARB_pixel_buffer_object, and disable broken imaging extension.Eric Anholt
While I haven't tested the imaging extension, this matches what 915 does.
2007-12-16[965] Move to using shared texture management code.Eric Anholt
This removes the delayed texture upload optimization from 965, in exchange for bringing us closer to PBO support. It also disables SGIS_generate_mipmap, which didn't seem to be working before anyway, according to the lodbias demo.
2007-12-15[965] Use shared intel_regions.c.Eric Anholt
This adds (so far) unused PBO functions, and holding the lock while writing to regions (which may be shared static screen regions).
2007-12-13[intel] Enable INTEL_DEBUG=bufmgr output in TTM mode as well as classic.Eric Anholt
2007-12-12[intel] Move bufmgr back to context instead of screen, fixing glthreads.Eric Anholt
Putting the bufmgr in the screen is not thread-safe since the emit_reloc changes. It also led to a significant performance hit from pthread usage for the attempted thread-safety (up to 12% of a cpu spent on refcounting protection in single-threaded 965). The motivation had been to allow multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
2007-12-10[965] Hook up DEBUG_BUFMGR output for bufmgr_fake.Eric Anholt
2007-12-07[965] Convert the driver to dri_bufmgr interface and enable TTM.Eric Anholt
This is currently believed to work but be a significant performance loss. Performance recovery should be soon to follow. The dri_bo_fake_disable_backing_store() call was added to allow backing store disable like bufmgr_fake.c did, which is a significant performance win (though it's missing the no-fence-subdata part). This commit is a squash merge of the 965-ttm branch, which had some history I wanted to avoid pulling due to noisiness and brokenness at many points for git-bisecting.
2007-11-19[965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.Eric Anholt
2007-10-30More vblank cleanups.Michel Dänzer
* Fix crash at context creation in most drivers supporting vblank. * Don't pass vblank sequence or flags to functions that get passed the drawable private already. * Attempt to initialize vblank related drawable private fields just once per drawable. May need more work in some drivers.
2007-10-29Refactor and fix core vblank supportJesse Barnes
Consolidate support for synchronizing to and retrieving vblank counters. Also fix the core vblank code to return monotonic MSC counters, which are required by some GLX extensions. Adding support for multiple pipes to a low level driver is fairly easy, the Intel 965 driver provides simple example code (see intel_buffers.c:intelWindowMoved()). The new code bumps the media stream counter extension version to 2 and adds a new getDrawableMSC callback. This callback takes a drawablePrivate pointer, which is used to calculate the MSC value seen by clients based on the actual vblank counter(s) returned from the kernel. The new drawable private fields are as follows: - vblSeq - used for tracking vblank counts for buffer swapping - vblFlags - flags (e.g. current pipe), updated by low level driver - msc_base - MSC counter from the last time the current pipe changed - vblank_base - kernel DRM vblank counter from the last time the pipe changed Using the above variables, the core vblank code (in vblank.c) can calculate a monotonic MSC value. The low level DRI drivers are responsible for updating the current pipe (by setting VBLANK_FLAG_SECONDARY for example in vblFlags) along with msc_base and vblank_base whenever the pipe associated with a given drawable changes (again, see intelWindowMoved for an example of this). Drivers should fill in the GetDrawableMSC DriverAPIRec field to point to driDrawableGetMSC32 and add code for pipe switching as outlined above to fully support the new scheme.
2007-10-26Merge branch '965-glsl'Zou Nan hai
Conflicts: src/mesa/drivers/dri/i965/brw_sf.h src/mesa/drivers/dri/i965/intel_context.c
2007-10-10fix force_s3tc_enable optionMrc Gran
2007-10-09 Non Square MatrixZou Nan hai
2007-09-27[965] Add batchbuffer dumping under INTEL_DEBUG=bat, like 915.Eric Anholt
2007-09-27Revert "WIP 965 conversion to dri_bufmgr."Eric Anholt
This reverts commit b2f1aa2389473ed09170713301b042661d70a48e. Somehow I ended up with my branch's save-this-while-I-work-on-master commit actually on master.
2007-09-27WIP 965 conversion to dri_bufmgr.Eric Anholt
2007-09-27[965] Remove AUB file support.Eric Anholt
This code existed to dump logs of hardware access to be replayed in simulation. Since we have real hardware now, it's not really needed.
2007-09-26 fix a bug in 965 ARB_occlusion_query,Zou Nan hai
fd.o bug #12132
2007-09-20Merge branch 'master' into i915-unificationEric Anholt
Conflicts: src/mesa/drivers/dri/common/dri_drmpool.c src/mesa/drivers/dri/i915tex/i915_vtbl.c src/mesa/drivers/dri/i915tex/intel_batchbuffer.c src/mesa/drivers/dri/i915tex/intel_context.c
2007-09-18 ARB_shader_object ARB_vertex_shader ARB_fragment_shader in 965-glsl branchZou Nan hai
2007-09-18fix double free in 965-glsl branchZou Nan hai
2007-08-29i965: store read drawable info in intel_context. Some OpenGLXiang, Haihao
operations are based on read drawable. fix bug#10136.
2007-08-02 EXT_texture_sRGB support on i965Zou Nan hai
2007-07-30 ARB sprite point support on i965Zou Nan hai
2007-07-04Merge branch 'master' of git+ssh://znh@git.freedesktop.org/git/mesa/mesa ↵Zou Nan hai
into 965-glsl
2007-06-21Merge branch 'origin' into i915-unificationEric Anholt
2007-05-31i965: Add pci info for 965GME/GLE chip.Wang Zhenyu
2007-05-17Convert i915tex to the new interface and make it compile.Eric Anholt
2007-04-12 Initial 965 GLSL supportZou Nan hai
2007-02-25Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2007-02-02Merge branch 'vbo-0.2'Keith Whitwell
Conflicts: src/mesa/main/texcompress_s3tc.c src/mesa/tnl/t_array_api.c
2007-02-02Add Intel 965GM chipset infoWang Zhenyu
2007-02-02Revert origin crestline pci id patchWang Zhenyu
2007-01-26Bug #9604: Fix a static buffer allocation failure.Eric Anholt
The pool that the static buffer got allocated from was sized by pitch * height, but the buffer generated from it had its size aligned to a tile boundary, so allocation failed if pitch * height wasn't aligned. However, the 2d driver ensures that the size ends at a tile boundary, so just pass the 2d driver's buffer size rather than calculating it.
2007-01-26Remove dead code causing a warning.Eric Anholt