Age | Commit message (Collapse) | Author | |
---|---|---|---|
2007-10-10 | Drop __DRInativeDisplay and pass in __DRIscreen pointers instead. | Kristian Høgsberg | |
Many DRI entry points took a __DRInativeDisplay pointer and a screen index as arguments. The only use for the native display pointer was to pass it back to the loader when looking up the __DRIscreen for the given screen index. Instead, let's just pass in the __DRIscreen pointer directly, which let's drop the __DRInativeDisplay type and the getScreen function. The assumption is now that the loader will be able to retrieve context from the __DRIscreen pointer when necessary. | |||
2007-10-04 | [965] Replace various alignment code with a shared ALIGN() macro. | Eric Anholt | |
In the process, fix some alignment issues: - Scratch space allocation was aligned into units of 1KB, while the allocation wanted units of bytes, so we never allocated enough space for scratch. - GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1. | |||
2007-10-04 | Replace bmBufferOffset usage in batchbuffer setup with OUT_RELOC. | Eric Anholt | |
This is in preparation for 965 TTM. | |||
2007-10-04 | Replace duplicated intel_reg.h with a shared header. | Eric Anholt | |
2007-10-04 | Replace some structure-based batch preparation with plain OUT_BATCH. | Eric Anholt | |
OUT_BATCH is far more amenable to the upcoming relocations being done for TTM support. | |||
2007-09-27 | [965] Add batchbuffer dumping under INTEL_DEBUG=bat, like 915. | Eric Anholt | |
2007-09-27 | Revert "WIP 965 conversion to dri_bufmgr." | Eric Anholt | |
This reverts commit b2f1aa2389473ed09170713301b042661d70a48e. Somehow I ended up with my branch's save-this-while-I-work-on-master commit actually on master. | |||
2007-09-27 | WIP 965 conversion to dri_bufmgr. | Eric Anholt | |
2007-09-27 | [965] Remove AUB file support. | Eric Anholt | |
This code existed to dump logs of hardware access to be replayed in simulation. Since we have real hardware now, it's not really needed. | |||
2007-09-27 | i965: handle all unfilled mode in clip stage. fix bug #12453 | Xiang, Haihao | |
2007-09-27 | fix ppracer and bzflag issue with clip optimization | Zou Nan hai | |
2007-09-27 | i915/i965 merge serer directories along lines for radeon/r200 | Dave Airlie | |
2007-09-26 | i965: The cube map texture coordinates must be devided by the | Xiang, Haihao | |
component with the largest absolute value before they are delivered. fix bug #12421 | |||
2007-09-26 | fix a bug in 965 ARB_occlusion_query, | Zou Nan hai | |
fd.o bug #12132 | |||
2007-09-24 | [i965] Bug #11812: Fix fwrite return value checks in AUB file code. | Roland Bär | |
2007-09-24 | fix fd.o bug #12217, recalcuate urb when clip plane size change | Zou Nan hai | |
2007-09-21 | Merge branch 'i915-unification' | Eric Anholt | |
This branch replaces the DRM pool interface used by i915tex with a "dri_bufmgr" interface in dri/common which may be set up to use either TTM or traditional static memory management according to what is available. The i915tex TTM code now requires an updated DDX which provides proper buffer objects for the static front/back/depth, instead of using fake buffers. The driver is now built as i915_dri.so, and should replace the old i915 driver shortly. | |||
2007-09-20 | Merge branch 'master' into i915-unification | Eric Anholt | |
Conflicts: src/mesa/drivers/dri/common/dri_drmpool.c src/mesa/drivers/dri/i915tex/i915_vtbl.c src/mesa/drivers/dri/i915tex/intel_batchbuffer.c src/mesa/drivers/dri/i915tex/intel_context.c | |||
2007-09-20 | i965: fix an error in brw_vs_tnl.c | Xiang, Haihao | |
if the state of TEXMAT is changed, the VS isn't updated. | |||
2007-09-14 | i965: align the address of the first element within | Xiang, Haihao | |
the index buffer. (fix#11910) | |||
2007-09-12 | i965: translate shadow compare function into correct | Xiang, Haihao | |
internal function to match the EXT_shadow_funs spec. fix bug#11925 | |||
2007-09-12 | i965: revert commit 1a15b2169ba6cb100627eb525a20a00537cfb6f0, | Xiang, Haihao | |
and keep the instruction state unchanged after calling brw_emit_tri_setup/brw_emit_line_setup when building setup thread for SF_UNFILLED_TRIS. | |||
2007-09-11 | Fix-up #includes to remove some -I options. | Brian | |
eg: #include "shader/program.h" and remove -I$(TOP)/src/mesa/program | |||
2007-09-11 | i965: take the secondary color into account when drawing | Xiang, Haihao | |
bitmap. fix#10688 | |||
2007-09-11 | i965: limit on LOD Bias, fix#11987 | Xiang, Haihao | |
2007-09-05 | i965: only take non-varying attribute into account when | Xiang, Haihao | |
compiling sf_prog. fix bug#11378 (which is introduced by commit d619cceea47dc3070ebb7f7ea4f8b6b31a672d38) | |||
2007-09-01 | i965: Correct build_lighting in i965 driver according to | Xiang, Haihao | |
commit 6dd98e9853a6984150aa47467112e016c40a4ab4. | |||
2007-08-31 | i965: Calculate the positional light in homogeneous coordinates. | Xiang, Haihao | |
fix bug#11009 | |||
2007-08-31 | optimize 965 clip | Zou Nan hai | |
1. increase clip thread number to 2 2. do cliptest for -rhw | |||
2007-08-31 | i965: Take the upper limitation on LOD into account. | Xiang, Haihao | |
2007-08-30 | Bug #10571: Fix 965 line clipping when neither vertex needs clipping. | David Moore | |
2007-08-29 | i965: store read drawable info in intel_context. Some OpenGL | Xiang, Haihao | |
operations are based on read drawable. fix bug#10136. | |||
2007-08-29 | i965: check NULL pointer. fix bug#12193 | Xiang, Haihao | |
2007-08-29 | i965: samplers group in fours in WM_STATE. fix bug#9415 | Xiang, Haihao | |
2007-08-28 | i965: flush batch buffer when getting the maximum. This makes | Xiang, Haihao | |
some 3D programs such as pymol work well. | |||
2007-08-17 | i965: align width/height for volume texture | Xiang, Haihao | |
2007-08-15 | i965: use BRW_TEXCOORDMODE_CLAMP instead of BRW_TEXCOORDMODE_CLAMP_BORDER | Xiang, Haihao | |
to implement GL_CLAMP | |||
2007-08-13 | i965: fix projtex_mask | Xiang, Haihao | |
projtex_mask is only an 8bit field, and wm.input_size_masks includes other attributes' information, therefore right shift is needed. | |||
2007-08-10 | i965: roland's DXTn format texture patch(bug10347) | Xiang, Haihao | |
2007-08-10 | i965/i915tex: applying right alignment to compressed texture, | Xiang, Haihao | |
which make small textures(4x4,2x2,1x1) work well. | |||
2007-08-10 | i965: set mt->cpp differently with compressed texture | Xiang, Haihao | |
2007-08-02 | Fix typo in logic for unalias2() | Keith Whitwell | |
2007-08-02 | fix fd.o bug #11804 | Zou Nan hai | |
glPolygonMode with point sprite on i965 | |||
2007-08-02 | Fix previous commit | Zou Nan hai | |
2007-08-02 | EXT_texture_sRGB support on i965 | Zou Nan hai | |
2007-08-01 | fix fd.o bug #11788, max point size | Zou Nan hai | |
2007-07-31 | i965: fix bad casts in do_blit_bitmap to support WindowPos correctly | Xiang, Haihao | |
2007-07-31 | i965: Use I16_UNORM instead of L16_UNORM (bug 11742) | Xiang, Haihao | |
2007-07-30 | ARB sprite point support on i965 | Zou Nan hai | |
2007-07-21 | Remove ctx->Point._Size and ctx->Line._Width. | Brian | |
The clamping for these values depends on whether we're drawing AA or non-AA points, lines. Defer clamping until drawing time. Drivers could compute and keep clamped AA and clamped non-AA values if desired. |