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(bug #16852, #16853)
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Conflicts:
src/mesa/drivers/dri/intel/intel_span.c
src/mesa/main/fbobject.c
This converts the i915 driver to use the GEM interfaces for object management.
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To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
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inst->TexSrcUnit is used as an index into program->SamplerUnits[] since
the commit ade508312c701ce89d3c2cd717994dbbabb4f207, and program->SamplerUnits
is a sampler-to-texture-unit mapping.
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Conflicts:
src/mesa/drivers/dri/common/dri_bufmgr.c
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
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should fix fd.o 14441
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This reverts commit b993d539a76e7f1446890a85e4b61deec4d4162d. The
patch was applied incorrectly. Actual fix coming soon. Sorry for the
noise.
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Numbers of destination depth registers corrected (destination stencil
register was sent as depth register).
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This disallows vertex shader texture sampling. See bugs 16157, 13838.
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Most of these were to ensure that caches got synchronized between 2d (or meta)
rendering and later use of the target as a source, such as for texture
miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(),
which just drops an MI_FLUSH. Most of the remainder were to ensure that
REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped.
Those are now replaced by automatically flushing those when dropping the lock.
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This disables the textured copy implementation on 965, which didn't appear
to work (mesa copypix demo, disable the blit path, move so that regions don't
overlap and textured is used, and you get garbage). If we resurrect this for
i965, I'd rather it used the 915-style metaops instead. Current metaops code
left in place so that whoever picks it up has a reference.
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Mesa demos tend to leave blending on but in GL_ONE/GL_ZERO, or
GL_SRC_ALPHA/GL_ONE_MINUS_SRC_ALPHA with a source alpha of 1.0.
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Both had some useful bits for the other.
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This is an API breakage only.
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Conflicts:
src/mesa/drivers/dri/common/dri_bufmgr.h
src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c
src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h
src/mesa/drivers/dri/intel/intel_ioctl.c
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Otherwise, since the MI_FLUSH at the end of every batch had been removed,
non-automatic-flushing chips (965) wouldn't get flushed and apps with static
rendering would get partial screen contents until the server's blockhandler
flush kicked in.
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This existed to get the icache flushed. However, GEM handles this for us
now for sure, and we had disabled it prematurely anyway.
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The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
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In classic mode googleearth triggered a case where vbos weren't getting accounted properly.
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Negative value means other errors, not aperture overflow. fix bug #15752
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The 32-bit immediate value in the i965 instruction word must contain two
copies of any 16-bit constants. brw_imm_uw and brw_imm_w just needed to
copy the value into both halves of the immediate value instruction field.
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e.g. bridge of fate.
If vs output is big, driver may fall back to use 8 urb entries for vs,
unfortunally, for some unknown reason, if vs is working at 4x2 mode,
8 entries is not enough, may lead to gpu hang.
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Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
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This reverts commit 3158e981f5f37768e9b04765704b9eaece8b899b.
rhw issue has gone away on IGD.
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It was flagging a last_bo update even when last_bo didn't change, but
another part was failing to update last_bo when it should have.
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