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path: root/src/mesa/drivers/dri/i965
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2008-02-27intel: Always use intelInitExtensions() for initializing extensions.Kristian Høgsberg
2008-02-26i965: Setup framebuffer texture in meta_draw_region.Kristian Høgsberg
With DRI2 we there is no screen region until a drawable is bound to the context. Set up the framebuffer texture in meta_draw_region instead which should also handle the case where the draw region changes as a result of resizing a redirected window or resizing the screen.
2008-02-26[965] Don't segfault on INTEL_DEBUG=batch when a surface buffer is NULL.Eric Anholt
2008-02-26[965] remove dead brw_parameter_list_state_flags.Eric Anholt
This was replaced by Mesa core code.
2008-02-25intel: Add missing include file to silence last couple of warnings.Kristian Høgsberg
2008-02-25i965: fix assertion failure caused by commit ↵Xiang, Haihao
dd1d66fc4ab5d7064113a2017a431c3461598b91.
2008-02-22intel: Merge intel_context.c from i915 and i965.Kristian Høgsberg
2008-02-22Merge {i915,i965}/intel_context.h as intel/intel_context.hKristian Høgsberg
2008-02-22Use drm_i915_sarea instead of drmI830Sarea and remove i830_common.hAlan Hourihane
2008-02-19 fix compile for previous commitZou Nan hai
2008-02-19[i965] fix broken glsl texdemo1Zou Nan hai
2008-02-15i965: don't swizzle fogcoord if FogOption is FOG_NONE.Xiang, Haihao
fix #10788 issue on 965.
2008-02-14i965: use setup attributes as inputs when allocating registersXiang, Haihao
for WM payload. fix #10767
2008-02-14[i965] flip point spriteZou Nan hai
2008-02-14[i965] gl_FrontFacing supportZou Nan hai
2008-02-14i965: remove unused hal hooksDave Airlie
These don't appear to have ever been used.
2008-02-13[965] Fix ARB_occlusion_query from intel_screen.c merge.Eric Anholt
It wasn't being initialized at screen setup, so we were getting stub entrypoints even though it was exposed as enabled. Fixes arbocclude mesa demo.
2008-02-13[intel] Fix 965 rendering with non-TTM by merging intel_ioctl between 915/965.Eric Anholt
The 965 path wasn't setting pClipRects for batch submission since it didn't want kernel cliprect handling before. The 915 path also grew the INTEL_NO_HW=1 option for testing just driver overhead.
2008-02-12[965] Remove stale brw_state_cache.c comment and function export.Eric Anholt
2008-02-07[965] Flush icache on new batch, not just new context.Eric Anholt
This is required since our buffer manager may now move our instruction-containing buffers at any batchbuffer emit.
2008-02-05i965: adjust the byte order of clear color. fix #14165Xiang, Haihao
2008-02-04[965] Convert brw_draw_upload to managing dri_bos, not gl_buffer_objects.Eric Anholt
This helps us avoid a bunch of mess with gl_client_arrays that we filled with unused data and confused readers.
2008-02-04[965] Remove dead structure in brw_draw_upload.c.Eric Anholt
2008-02-04[965] Move temporary vbo array storage into the function using it.Eric Anholt
2008-02-04[965] Remove dead brw_vertex_element members.Eric Anholt
2008-02-04[965] Add a wrapper around interleaved copy_array_to_vbo_array for profiling.Eric Anholt
If compiled with optimization, it shouldn't appear at all, and helps me for now.
2008-02-04[965] Avoid overloaded use of the term 'input' for clarity.Eric Anholt
2008-02-04[965] Replace VEP/VBP state structures with inline batch emits.Eric Anholt
2008-02-03i965: fix potential NULL pointer dereference. The third regionXiang, Haihao
isn't created at all for 965
2008-02-01[965] Fix indentation.Eric Anholt
2008-02-01[965] Replace XXX comment about constant swizzle with an assert.Eric Anholt
2008-02-01[965] Fix some indentation in brw_vs_tnl.c.Eric Anholt
2008-02-01i965: Don't emit state if fall back to software rendering. fix #14116Xiang, Haihao
2008-01-31[i965] renable regative rhw testZou Nan hai
2008-01-29i965: new integrated graphics chipset supportXiang, Haihao
2008-01-25i965: valid message length includes message header.Xiang, Haihao
2008-01-25i965: re-define the type of reg.loopcount.Xiang, Haihao
avoid some issues such that 1 + (-2) gets a big positive value.
2008-01-19[965] Fix WM unit cache keying that broke line stipple and polygon offset.Eric Anholt
2008-01-18[965] Do a little bit rotation in state hash to reduce collisions.Eric Anholt
This was around 3% improvement in OA.
2008-01-17[intel] Make the no_rast option be standard driconf instead of INTEL_NO_RAST.Eric Anholt
2008-01-17[965] Fix whitespace in c9b1fef0c9c5018efd825c42782f19ad0618696aEric Anholt
2008-01-17[965] Fix potential segfaults from bad realloc.Eric Anholt
C has no order of evaluation restrictions on function arguments, so we attempted to realloc from new-size to new-size.
2008-01-17i965: always call dri_emit_reloc when creating clip unit stateXiang, Haihao
This fix ensures it gets the starting location of the clip program if a clip unit state is same as a unit which is created when metaops is actived and it doesn't impact metaops because the clip state offset isn't emitted when metaops is actived.
2008-01-16[965] Fix inversion of SLT/SGE results in vertex programs.Eric Anholt
The WM code had this right, so copy its behavior. This reverts a flipping of the arguments to SLT in brw_vs_tnl which came in with the GLSL code that probably occurred to work around the flipped results, and brings the code back in line with t_vp_build.c.
2008-01-16[965] Rename depth_mask in CC key to depth_write, since it's a boolean enable.Eric Anholt
2008-01-16[965] Fix the type of alpha_ref in CC key, fixing ppracer rendering.Eric Anholt
2008-01-15 i965: fix an assert fail in brw_new_batchZou Nan hai
2008-01-14[965] Force a new vertex upload buffer at new batch time.Eric Anholt
Otherwise, we could choose to upload into the temporary VBO that we just fired off to the hardware. Good for a 60% OA performance improvement.
2008-01-10[965] Remove an open-coded memcpy.Eric Anholt
2008-01-10[965] Improve performance by allocating CURBE buffers a page at a time.Eric Anholt
Since each one is only 64b, and kernel allocations are a page anyway, this lets us reduce buffer allocation by packing many CURBEs into one buffer, for each batchbuffer submitted. Improves openarena performance by around 10%.
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