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This fixes
brw_eu_emit.c:179: validate_reg: Assertion `width == 1' failed.
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Just like everywhere else, I never trust my constant uploads to
correctly put constants in the right places, even though that's so
rarely where the issue is.
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It's mostly like gen4 message descriptor setup, except that the sizes
of type/control changed to be like gen5. Fixes 21 piglit cases on
gm45, including the regressions in bug #32311 from increased VS
constant buffer usage.
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This makes conformance tests stable on sandybridge D0 to track
multisample state before SF/WM state.
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Determine header present for fb write by msg length is not right
for SIMD16 dispatch, and if there're more output attributes, header
present is not easy to tell from msg length. This explicitly adds
new param for fb write to say header present or not.
Fixes many cases' hang and failure in GL conformance test.
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The SNB alt-mode math does the denorm and inf reduction even for a
"raw MOV" like we do for g0 message header setup, where we are moving
values that aren't actually floats. Just use UD type, where raw MOVs
really are raw MOVs.
Fixes glxgears since c52adfc2e1d130effea940e75690897eb5d3ceaa, but no
piglit tests had regressed(!)
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This matches how we did the math instructions pre-gen6, though it
applies to non-math as well.
Fixes vp1-LIT test 2 (degenerate case: 0 ^ 0 -> 1)
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This is still awful, but my ability to care about reworking the old
backend so we can just get a temporary value into a POW is awfully low
since the new backend does this all sensibly.
Fixes:
fp1-LIT test 1
fp1-LIT test 3 (case x < 0)
fp1-POW test (exponentiation)
fp-lit-mask
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Fixes glsl-bug-22603.
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Fixes fp-arb-fragment-coord-conventions-none
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RNDD isn't one of the instructions that can do conversion from
execution type to destination type.
Fixes glsl-vs-arrays-3.
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There are exceptions to the table for depth texturing or rendering to
not-quite-supported formats thanks to the non-orthogonal component
selection for surface formats, but it's still a lot simpler.
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VS places color attributes together so that SF unit can fetch the right
attribute according to object orientation. This fixes light issue in
mesa demo geartrain, projtex.
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Fixes depth-tex-modes-rg.
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Fixes this GCC warning.
brw_fs.cpp: In function 'brw_reg brw_reg_from_fs_reg(fs_reg*)':
brw_fs.cpp:3255: warning: 'brw_reg' may be used uninitialized in this function
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This is said to be required in the spec, even when you aren't doing writes.
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This doesn't actually fix border color on Ironlake, but it appears to
be a requirement, and gen6 needs it too.
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Last minute change for gen6 with 0 used params dropped the multiply.
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This eases the gen6 implementation, which can only handle up to 32
registers of constants, while likely not penalizing real apps using
reladdr since all of those I've seen also end up hitting the pull
constant buffer. On gen6, the constant map means that simple NV VPs
fit under the 32-reg limit and now succeed. Fixes around 10 testcases.
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Fixes:
fp-kil
fp-generic/kil-swizzle.
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Fixes:
fbo-drawbuffers2-blend
fbo-drawbuffers2-colormask
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This will let us get EXT_draw_buffers2 blending and colormasking working.
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Fixes glean/maskedClear
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Fixes glean/blendFunc
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Fixes:
glean/glsl1-! (not) operator (1, fail)
glean/glsl1-! (not) operator (1, pass)
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With the change of extended math from having the arguments moved into
mrfs and handed off through message passing to being directly hooked
up to the EU, it looks like the piece for doing source modifiers
(negate and abs) was left out.
Fixes:
fog-modes
glean/fp1-ARB_fog_exp test
glean/fp1-ARB_fog_exp2 test
glean/fp1-Computed fog exp test
glean/fp1-Computed fog exp2 test
ext_fog_coord-modes
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This can significantly ease thinking about the asm.
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Previously the code only handled scalars and vectors. This new code
is modeled somewhat after similar code in ir_to_mesa.
Reviewed-by: Eric Anholt <eric@anholt.net>
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gen6 builtin RSQ apparently clamps negative values to 0 instead of
returning the RSQ of the absolute value like ARB_fragment_program
desires and pre-gen6 apparently does.
Fixes:
glean/fp1-RSQ test 2 (reciprocal square root of negative value)
glean/vp1-RSQ test 2 (reciprocal square root of negative value)
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We get saturate as an argument to brw_math() instead of as compile
state, since that's how the pre-gen6 send instructions work. Fixes
fp-ex2-sat.
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This is the push constant buffer, not the pull constants.
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Be sure polygon stipple mode is updated. This fixes 'gamma' demo.
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It is used for point width on vertex. This fixes mesa demo spriteblast and pointblast.
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It was only used for gen6 fragment programs (not GLSL shaders) at this
point, and it was clearly unsuited to the task -- missing opcodes,
corrupted texturing, and assertion failures hit various applications
of all sorts. It was easier to patch up the non-glsl for remaining
gen6 changes than to make brw_wm_glsl.c complete.
Bug #30530
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Since the 8-wide first-quarter and 16-wide first-half have the same
bit encoding, we now need to track "do you want instruction
compression" in the compile state.
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The FS backend is fine with register level granularity. But for the
brw_wm_emit.c backend, it expects pairs of regs to be used for the
constants, because the whole world is pairs of regs. If an odd number
got used, we went looking for interpolation in the wrong place.
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We were accidentally doing a float-to-uint conversion.
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We were trying to do the implied move even when we'd already manually
moved the real header in place.
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In the SF and brw_fs.cpp fixes to set up interpolation sanely on gen6,
the setup for 16-wide interpolation was left behind. This brings
relative sanity to that path too.
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Fixes many assertion failures in that path.
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Payload reg setup on gen6 depends more on the dispatch width as well
as the uses_depth, computes_depth, and other flags. That's something
we want to decide at compile time, not at cache lookup. As a bonus,
the fragment shader program cache lookup should be cheaper now that
there's less to compute for the hash key.
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