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path: root/src/mesa/drivers/dri/i965
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2009-08-13i965: fix cube map on IGDNGXiang, Haihao
2009-08-12Merge branch 'new-frag-attribs'Brian Paul
This branch introduces new FRAG_ATTRIB_FACE and FRAG_ATTRIB_PNTC fragment program inputs for GLSL gl_FrontFacing and gl_PointCoord. Before, these attributes were packed with the FOG attribute. That made things complicated elsewhere.
2009-08-12i965: Make the cube mapping RCP use a writemask.Eric Anholt
Fixes cube mapping since the scalar changes.
2009-08-12i965: Allocate destination registers for GLSL TEX instructions contiguously.Eric Anholt
This matches brw_wm_pass*.c behavior, and fixes the norsetto shadow demo. Bug #19489
2009-08-12i965: drop dead scalar handling in GLSL.Eric Anholt
2009-08-12i965: Correct brw_wm_nr_args for WM_DELTAXY and WM_PIXELXY.Eric Anholt
2009-08-12i965: Drop GLSL ABS code, which is translated away in brw_wm_fp.Eric Anholt
2009-08-12i965: Drop code for emitting OPCODE_SUB, since brw_wm_fp.c makes it an ADD.Eric Anholt
2009-08-12i965: Store the dispatch width in the WM compile struct.Eric Anholt
I'll be using this in merging brw_wm_emit.c and brw_wm_glsl.c
2009-08-12i965: Handle scalar result swizzling in shared GLSL/non-GLSL code.Eric Anholt
This is preparation for merging of brw_wm_glsl.c and brw_wm_emit.c, and glsl.c doesn't swizzle channel results around.
2009-08-12i965: Flag ARL-using programs as requiring brw_wm_glsl.cEric Anholt
This doesn't fix the glean testcase, but I guess it provides hope.
2009-08-12i965: Remove some unused WM opcode args.Eric Anholt
2009-08-12i965: Avoid re-uploading the index buffer when we don't need to.Eric Anholt
No performance difference proven at 95% confidence with my GLSL demo (n=10).
2009-08-12vbo: Avoid extra validation of DrawElements.Eric Anholt
This saves mapping the index buffer to get a bounds on the indices that drivers just drop on the floor in the VBO case (cache win), saves a bonus walk of the indices in the CheckArrayBounds case, and other miscellaneous validation. On intel it's a particularly a large win (50-100% in my app) because even though we let the indices stay in both CPU and GPU caches, we still end up waiting for the GPU to be done with the buffer before reading from it. Drivers that want the min/max_index fields must now check index_bounds_valid and use vbo_get_minmax_index before using them.
2009-08-12i965: Use _MaxElement instead of index-calculated min/max for VBO bounds.Eric Anholt
2009-08-07i965: Add a note justifying domain choice for the SF VP.Eric Anholt
2009-08-07i965: Replace the subroutine-skipping jump in VS with a NOP if it's a NOP.Eric Anholt
This showed a 1.9% (+/-.3%, n=3) improvement in OA performance with high geometry settings.
2009-08-07i965: minor context commentsBrian Paul
2009-08-05i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt
For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603.
2009-08-04i965: Fix dangerous warning I let slip in.Eric Anholt
2009-08-04i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt
Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be useful for the looping code. Bug #18992
2009-08-04i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt
Previously, we'd be branching based on whatever condition code happened to be laying around.
2009-08-04i965: Don't set pop_count in the reserved MBZ area of IF statements.Eric Anholt
2009-08-04i965: Print out ELSE and ENDIF src1 arguments like IF does.Eric Anholt
2009-08-04intel: Add support for EXT_provoking_vertex.Eric Anholt
2009-08-04i965: Spell "conditional" correctly.Eric Anholt
2009-08-04i965: Hook up the disassembler for INTEL_DEBUG={wm,vs}.Eric Anholt
I was getting tired of doing the dance of INTEL_DEBUG=batch, copying it out, and running intel-gen4disasm on it.
2009-08-04i965: Initial import of disasm code from intel-gen4asm.Eric Anholt
There's a bunch of stuff from gen4asm and gpu-tools that we probably want to make into a library instead of cargo-culting it around.
2009-08-04i965: warning fixEric Anholt
2009-08-04i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt
Bug #20821
2009-08-03i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt
This avoids sending a bad buffer address to the GPU due to programmer error, and is permitted by the ARB_vbo spec. Note that we still have the opportunity to dereference past the end of the GPU, because we aren't clipping to a correct _MaxElement, but that appears to be harder than it should be. This gets us the 90% solution. Bug #19911.
2009-08-03i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt
See comment on Vertex URB Entry Read Length for VS_STATE. This, combined with the previous three commits, fixes #22945.
2009-08-03i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt
This fix is just from code and docs inspection, but it may fix hangs on some applications.
2009-08-03i965: Don't emit bad packets when no VBs are referenced.Eric Anholt
It appears that sometimes Mesa (and I suppose a VS could as well) emits a program which references no vertex data, and thus we end up with nr_enabled == 0 even though some VBs are enabled. We'd end up emitting VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs. Bug #22945 (wine with an uncompiled VS)
2009-08-03i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt
The code duplication bothered me.
2009-07-31Rename TGSI LOOP instruction to better match theri usage.Michal Krol
The LOOP/ENDLOOP pair is renamed to BGNFOR/ENDFOR as its behaviour is similar to a C language for-loop. The BGNLOOP2/ENDLOOP2 pair is renamed to BGNLOOP/ENDLOOP as now there is no name collision.
2009-07-30i965: Postpone ff_sync message in CLIP kernel on IGDNGXiang, Haihao
In addition, it guarantees ff_sync message is issued
2009-07-29mesa: add new FRAG_ATTRIB_FACE and FRAG_ATTRIB_PNTC fragment program inputsBrian Paul
Previously, the FOGC attribute contained the fragment fog coord, front/back- face flag and the gl_PointCoord.xy values. Now each of those things are separate fragment program attributes. This simplifies quite a few things in Mesa and gallium. Need to test i965 driver and fix up point coord handling in the gallium/draw module...
2009-07-20i965: Don't clip everything if FRONT_AND_BACK culling while culling disabled.Eric Anholt
Fixes everything-black with meta_clear_tris on quake4-mpdemo and doom3-demo. Bug #18844, 22077.
2009-07-16i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt
2009-07-15i965: the offset of any branch/jump instruction is in unit of 64bits on IGDNGXiang, Haihao
2009-07-13i965: add support for new chipsetsXiang, Haihao
1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
2009-07-07i965: Remove BRW_NEW_INPUT_VARYINGEric Anholt
This state flag has been unused since the ffvertex_prog move to core.
2009-07-02i965: fixes for JMPIXiang, Haihao
1. the data type of <src1> (JMPI offset) must be D 2. execution size must be 1 3. NoMask 4. instruction compression isn't allowed.
2009-06-30i965: Increase G4X default VS URB allocation to actually allow 32 threads.Eric Anholt
This improves the performance of my GLSL demo by 30%. It also fixes the VS deadlock that ut2004 had, for reasons I can't explain. Bug #21330.
2009-06-30i965: first attempt at handling URB overflow when there's too many vs outputsBrian Paul
If we can't fit all the VS outputs into the MRF, we need to overflow into temporary GRF registers, then use some MOVs and a second brw_urb_WRITE() instruction to place the overflow vertex results into the URB. This is hit when a vertex/fragment shader pair has a large number of varying variables (12 or more). There's still something broken here, but it seems close...
2009-06-30i965: use BRW_MAX_MRFBrian Paul
2009-06-30i965: use BRW_MAX_GRF, BRW_MAX_MRFBrian Paul
2009-06-30i965: move BRW_MAX_GRF, define BRW_MAX_MRFBrian Paul
2009-06-30i965: defined BRW_MAX_MRFBrian Paul