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path: root/src/mesa/drivers/dri/i965
AgeCommit message (Expand)Author
2011-01-20intel: Fix typeos from 3d028024 and 790ff232Ian Romanick
2011-01-20i965: Set correct values for range/precision of fragment shader typesIan Romanick
2011-01-19i965/fs: Take the shared mathbox into account in instruction scheduling.Eric Anholt
2011-01-19i965/fs: Add a helper function for detecting math opcodes.Eric Anholt
2011-01-19i965/fs: Assign URB/CURB register numbers after instruction scheduling.Eric Anholt
2011-01-19i965/fs: Add an instruction scheduler.Eric Anholt
2011-01-19i965/fs: Add a helper for detecting texturing opcodes.Eric Anholt
2011-01-18i965: Fix a comment typo.Eric Anholt
2011-01-18i965: Fix a bug in i965 compute-to-MRF.Eric Anholt
2011-01-17i965: Fix dead pointers to fp->Parameters->ParameterValues[] after realloc.Eric Anholt
2011-01-16i965: add support for EXT_texture_sRGB_decodeDave Airlie
2011-01-15mesa: begin implementation of GL_ARB_draw_buffers_blendBrian Paul
2011-01-14i965: Replace broken handling of dead code with an assert.Eric Anholt
2011-01-14i965: Add an invalidation of live intervals after register splitting.Eric Anholt
2011-01-14i965: fix fbo-srgb on i965.Dave Airlie
2011-01-13i965: Remove unnecessary headers.Vinson Lee
2011-01-12i965/fs: Do flat shading when appropriate.Eric Anholt
2011-01-12i965: Clarify when we need to (re-)calculate live intervals.Eric Anholt
2011-01-12i965/vs: When MOVing to produce ABS, strip negate of the operand.Eric Anholt
2011-01-12i965/fs: When producing ir_unop_abs of an operand, strip negate.Eric Anholt
2011-01-11i965: Tighten up the check for flow control interfering with coalescing.Eric Anholt
2011-01-11i965: Remove dead fallback for stencil _Enabled but no stencil buffer.Eric Anholt
2011-01-10i965: Use a new miptree to avoid software fallbacks due to drawing offset.Eric Anholt
2011-01-10Revert "intel: Always allocate miptrees from level 0, not tObj->BaseLevel."Eric Anholt
2011-01-10i965: Add #defines for HiZ and separate stencil buffer commands.Kenneth Graunke
2011-01-10i965: Add new HiZ related bits to WM_STATE.Kenneth Graunke
2011-01-10i965: Rename more #defines to 3DSTATE rather than CMD or CMD_3D.Kenneth Graunke
2011-01-10i965: Remove unused #defines which only contain the sub-opcode.Kenneth Graunke
2011-01-07intel: Add a vtbl hook for determining if a format is renderable.Eric Anholt
2011-01-07i965: Avoid double-negation of immediate values in the VS.Eric Anholt
2011-01-06i965: Rename various gen6 #defines to match the documentation.Kenneth Graunke
2011-01-05intel: Always allocate miptrees from level 0, not tObj->BaseLevel.Eric Anholt
2011-01-05intel: Clarify first_level/last_level vs baselevel/maxlevel by deletion.Eric Anholt
2011-01-05i965: Simplify the renderbuffer setup code.Eric Anholt
2011-01-04i965: Add support for SRGB DXT1 formats.Eric Anholt
2011-01-04i965: Use last vertex convention for quad provoking vertex on sandybridgeZhenyu Wang
2011-01-04i965: Correct comment for gen6 fb write control message settingZhenyu Wang
2011-01-04i965: Fix provoking vertex select in clip state for sandybridgeZhenyu Wang
2010-12-28i965: Do lowering of array indexing of a vector in the FS.Eric Anholt
2010-12-28i965: Fix regression in FS comparisons on original gen4 due to gen6 changes.Eric Anholt
2010-12-28i965: Factor out the ir comparision to BRW_CONDITIONAL_* code.Eric Anholt
2010-12-28i965: Fix occlusion query on sandybridgeZhenyu Wang
2010-12-28Revert "i965: upload multisample state for fragment program change"Zhenyu Wang
2010-12-27i965: don't spawn GS thread for LINELOOP on SandybridgeXiang, Haihao
2010-12-27i965: Flatten if-statements beyond depth 16 on pre-gen6.Kenneth Graunke
2010-12-24i965: use align1 access mode for instructions with execSize=1 in VSXiang, Haihao
2010-12-24i965: fix register region descriptionXiang, Haihao
2010-12-23i965: Remove unnecessary headers.Vinson Lee
2010-12-23i965: Keep around a copy of the VS constant surface dumping code.Eric Anholt
2010-12-23i965: Correct the dp_read message descriptor setup on g4x.Eric Anholt
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