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path: root/src/mesa/drivers/dri/i965
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2010-07-26i965: Clean up a few magic numbers to use brw_defines.h defs.Eric Anholt
2010-07-26i965: Use MIN2, MAX2 instead of rolling our own.Eric Anholt
2010-07-26i965: Fold the "is arithmetic" bit of 965 opcodes into the opcode list.Eric Anholt
2010-07-26i965: Remove some duped register size/count definitionsEric Anholt
2010-07-26i965: Move the GRF-to-MRF optimizations to brw_optimize.c.Eric Anholt
2010-07-26i965: Improve (i.e. remove) some grf-to-mrf unnecessary movesBenjamin Segovia
Several routines directly analyze the grf-to-mrf moves from the Gen binary code. When it is possible, the mov is removed and the message register is directly written in the arithmetic instruction Also redundant mrf-to-grf moves are removed (frequently for example, when sampling many textures with the same uv) Code was tested with piglit, warsow and nexuiz on an Ironlake machine. No regression was found there Note that the optimizations are *deactivated* on Gen4 and Gen6 since I did test them properly yet. No reason there are bugs but who knows The optimizations are currently done in branch free programs *only*. Considering branches is more complicated and there are actually two paths: one for branch free programs and one for programs with branches Also some other optimizations should be done during the emission itself but considering that some code is shader between vertex shaders (AOS) and pixel shaders (SOA) and that we may have branches or not, it is pretty hard to both factorize the code and have one good set of strategies
2010-07-26i965: Allow VS MOVs to use immediate constants.Eric Anholt
Clarifies program assembly, and with a little tweak to always use constant_map, we could cut down on constant buffer payload.
2010-07-23i965: Cleanly fail programs with unsupported array access.Eric Anholt
This should be more useful for developers and for bug triaging than just generating wrong code.
2010-07-23i965: Add support for VS relative addressing of temporary arrays.Eric Anholt
Fixes glsl-vs-arrays. Bug #27388.
2010-07-22i965: Respect VS/VP point size result when enabled.Eric Anholt
Fixes glsl-vs-point-size.
2010-07-22i965: Fix the disasm output for da16 src widths.Eric Anholt
This has confused me twice now. It's a fixed width of 4 (usually a region description of <4,4,1>), not 1. If it was 1, we'd have been skipping all over register space.
2010-07-22i965: Avoid extra MOV in VS indirect register reads.Eric Anholt
2010-07-22i965: Fix up VS temporary array access for fixed index offset != 0.Eric Anholt
2010-07-21i965: In the VS, multiply the address reg by the appropriate register size.Eric Anholt
The ARL value is increments of vec4 in the register file. But PROGRAM_TEMPORARY or PROGRAM_INPUT are stored as vec4s interleaved between the two verts being executed (thus a vec8 each), compared to PROGRAM_STATE_VAR being packed vec4s. Fixes: glsl-vs-arrays-2 glsl-vs-mov-after-deref (without regressing glsl-vs-arrays-3)
2010-07-21i965: Clean up brw_dp_READ_4_vs() now that it has fewer options to support.Eric Anholt
2010-07-21i965: Support relative addressed VS constant reads using the appropriate msg.Eric Anholt
The previous support was overly complicated by trying to use the same 1-OWORD message for both offsets.
2010-07-21i965: Fix the DP read msg_control definitions other than plain OWORD.Eric Anholt
2010-07-21i965: Clean up dead code from the VS get_constant/get_reladdr_constant split.Eric Anholt
2010-07-21i956: Set the execution size correctly for scratch space writes.Eric Anholt
Otherwise, the second half isn't written, and we end up reading back black. Fixes the remaining junk drawn in glsl-max-varyings, and will likely help with a number of large real-world shaders.
2010-07-21i965: Set the GEM domain flags for the scratch space.Eric Anholt
They go into the render cache, so while we don't care about their contents after execution, failing to note them could cause the writes to be flushed over important buffer contents later.
2010-07-21i965: Use the pretty define for 4-oword DP reads.Eric Anholt
2010-07-21i965: Set the send commit bit on register spills as required pre-gen6.Eric Anholt
Otherwise, the subsequent read may not get the written value.
2010-07-21i965: Add disasm for dataport reads (register unspilling).Eric Anholt
2010-07-21i965: Remove an unused variable.Carl Worth
To quiet a compiler warning.
2010-07-19i965: Mostly fix glsl-max-varyings.Eric Anholt
There was confusion on both the size of message we can send, and on what the URB destination offset means. The remaining problems appear to be due to spilling of regs in the fragment shader being broken.
2010-07-19i965: Clean up message register setup in emit_vertex_write().Eric Anholt
2010-07-19i965: Reduce repeated calculation of the attribute-offset-in-VUE.Eric Anholt
This cleans up some chipset dependency sprinkled around, and fixes a potential overflow of the attribute offset array for many vertex results.
2010-07-19i965: Clarify the nr_regs calculation in brw_clip.cEric Anholt
2010-07-19i965: Don't set up VUE space for the disabled user clip distances on gen6.Eric Anholt
2010-07-08i965: Add disasm for SEND mlen/rlen on Sandybridge.Eric Anholt
2010-07-08i965: Add 'wait' instruction supportZhenyu Wang
When EU executes 'wait' instruction, it stalls and sets notification register state. Host can issue MMIO write to clear notification register state to allow EU continue on executing again. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2010-07-08i965: Fix disasm of a SEND's mlen and rlen on Ironlake.Eric Anholt
2010-07-08i965: Add decode for Sandybridge DP write messages.Zhenyu Wang
2010-07-08i965: Add definitions for Sandybridge DP write/read messages.Zhenyu Wang
2010-06-23Merge branch 'shader-file-reorg'Brian Paul
1. Move all GL entrypoint functions and files into src/mesa/main/ This includes the ARB vp/vp, NV vp/fp, ATI fragshader and GLSL bits that were in src/mesa/shader/ 2. Move src/mesa/shader/slang/ to src/mesa/slang/ to reduce the tree depth 3. Rename src/mesa/shader/ to src/mesa/program/ since all the remaining files are concerned with GPU programs. 4. Misc code refactoring. In particular, I got rid of most of the GLSL-related ctx->Driver hook functions. None of the drivers used them. Conflicts: src/mesa/drivers/dri/i965/brw_context.c
2010-06-18i965: Fix the name of aa_coverage_slope in the improved AA line params.Eric Anholt
2010-06-14i965: Remove unnecessary header.Vinson Lee
2010-06-14i965: Fix surface state dumping with INTEL_DEBUG=batch.Eric Anholt
I broke this with the state streaming changes.
2010-06-14i965: correct the gen6 line stipple enable define.Zhenyu Wang
2010-06-12i965: Fix gen6 front cull mode.Eric Anholt
2010-06-12i965: Use the new message header format for FF_SYNC on gen6.Zhenyu Wang
2010-06-12i965: Add support for math instructions in the gen6 WM.Zhenyu Wang
2010-06-12i965: Set the correct WM GRF start reg on gen6.Zhenyu Wang
2010-06-12i965: Update gen6 paths for the streaming rework.Eric Anholt
2010-06-12i965: Stream out CC unit state.Eric Anholt
before: [ # ] backend test min(s) median(s) stddev. count [ 0] gl firefox-talos-gfx 31.791 32.287 1.11% 6/6 after: [ 0] gl firefox-talos-gfx 31.198 31.675 0.96% 6/6
2010-06-12i965: Remove unnecessary header.Vinson Lee
2010-06-11i965: Remove the surface key used to generate constant surfaces.Eric Anholt
We had to fill out all that junk when using the cache, but no more.
2010-06-11i965: Warning fixes from the i965-streaming merge.Eric Anholt
2010-06-11i965: Use the state base address to avoid relocations.Eric Anholt
This makes the binding table code simpler, and is required for gen6, which requires binding table addresses to be under 64k offset from the surface state base addr. No significant change in performance on firefox-talos-gfx.
2010-06-11i965: GC the last two arguments to brw_cache_data.Eric Anholt
Now that the binding table is streamed indirect state, they were always NULL/0.
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