| Age | Commit message (Collapse) | Author |
|---|
|
Fixes 4 piglit tests about min, max, and clamp.
|
|
When it says it sets the LSB, that's not just a hint as to where the
result goes. Only the LSB is modified. Fixes 20 piglit cases.
|
|
When we're trying to do integer ops, handing a float in doesn't help.
|
|
Fixes:
glsl-fs-any.
glsl1-integer division with uniform var
|
|
Fixes glsl-fs-mod.
|
|
Fixes glsl-fs-neg and 5 other tests.
|
|
10 more piglit tests pass.
|
|
20 more piglit tests pass.
|
|
|
|
glsl-algebraic-rcp-rsq managed to use 33 registers, and we claimed to
only use 32, so the write to g32 would go stomping over the precious
g0 of some other thread.
|
|
This wouldn't catch the last failure fixed in them, because we don't
validate assignments well (due to the fact that we've got a pretty
glaring inconsistency in how we handle assignment writemasking), but
it could catch other failure we may produce.
|
|
|
|
|
|
We weren't smearing a component of a split RHS out to reach an unsplit
LHS's writemask, so gl_FragColor (always unsplit) would often get
uninitialized values.
Fixes: glsl-algebraic-add-add-1 (and probably many others).
|
|
+269 piglits
|
|
It hangs the GPU due to FB_WRITE handling being incomplete. There are
bigger issues to handle first.
|
|
|
|
I'm also fixing this upstream in libdrm, but this avoids new libdrm
dependency for the moment.
|
|
This should make debugging way easier, as now we have context for
reading large programs.
|
|
|
|
At least some tests, like glsl-vs-sign, now work.
|
|
This can successfully emit a real program that generates magenta now.
|
|
Our channel-expressions and vector-splitting changes now happen into a
private copy of the IR that we maintain for ourselves. Uniform
assignment still happens by the core, so we continue using Mesa IR
generation not just for swrast fallbacks but also for uniform values
(since there's no storage for their contents other than
shader_program->FragmentProgram->Parameters->ParameterValues). And
most importantly, at the moment no actual codegen is hooked up other
than emitting our favorite color to the framebuffer.
|
|
Combined with the previous pass, this lets other optimization passes
do their work thanks to ir_tree_grafting. Still have regression in
instruction count with INTEL_NEW_FS, but register count is even
better.
|
|
This is a step towards implementing a GLSL IR backend for the 965
fragment shader. Because it has downsides with the current codegen,
it is hidden under the environment variable INTEL_NEW_FS.
This results in an increase in instruction count at the moment (1444
-> 1752 for glsl-fs-raytrace, 345 -> 359 on my demo), because dot
products are turned into a series of multiplies and adds instead of a
custom expansion of MULs and MACs, and by not splitting the variable
types up we don't get tree grafting and thus there are extra moves of
temporary storage. However, register count drops for the non-GLSL
path (64 -> 56 on my demo shader) because the register allocator sees
all the sub-operations.
|
|
|
|
Fixes: glsl-vs-varying-array
|
|
Shader inputs appear in source registers, not dst registers. Catches
unsupported shaders in glsl-fs-varying-array and Humus
RaytracedShadows.
|
|
Texcoords in AmbientApertureLighting were getting trashed since the
move of math arguments to implied moves, due to the logic for
detecting ALU message reg writes overriding the logic for SEND
implicit message reg writes.
|
|
|
|
|
|
My merge of Zhenyu's patch on top of my previous patches broke it by
my code expecting simd16 single write and Zhenyu's simd8 path being
disabled by mine. Merge the two for success.
|
|
The docs claim two conflicting things: One, that a scalar source is
supported. Two, source hstride must be 1 and width must be exec size.
So splat a constant argument out into a full reg to operate on, since
violating the second set of constraints is clearly failing.
The alternative here might be to do a 1-wide exec on a constant
argument for math1. It would probably save cycles too. But I'll
leave that for the glsl2-965 branch.
Fixes glsl-algebraic-div-one-2.shader_test.
|
|
Fixes glsl-algebraic-add-add-1.
|
|
|
|
Only 8 out of the up to 13 regs are for source/dest depth, so the name
wasn't particularly appropriate. Note that this doesn't count the
constant or URB payload regs. Also, don't pre-divide by 2, so it's
actually a number of registers.
|
|
|
|
|
|
|
|
|
|
Whenever the accumulator results are needed, this bit must be set.
|
|
|
|
|
|
This makes reading the code easier when matching up to the specs,
which also use this format.
|
|
The SIMD16 message no longer has the goofy interleaved format that
made Compr4 compression necessary before.
|
|
format ‘%d’ expects type ‘int’, but argument 2 has type ‘long int’
|
|
Otherwise, we might end up with the if stack pointing at the wrong
place. Fixes GPU hang with glsl-vs-if-loop.
|
|
Fixes glsl-vs-if-nested (70.0 is not <= 70.000648 thanks to the
swizzle bits getting set). Some safety checks are added to make sure
this doesn't happen again as we increase the usage of immediate values
in program generation.
|
|
We'll need to use the HALT instruction to do this right, like returns
from other functions.
|
|
Fixes glsl-vs-dot-vec2.
|
