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path: root/src/mesa/drivers/dri/i965
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2008-07-16Remove redundant initalization of MaxTextureUnitsIan Romanick
2008-07-11drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt
2008-07-08i965: official name for GM45 chipsetXiang, Haihao
2008-07-02set ctx->Const.MaxVertexTextureImageUnits = 0Brian Paul
This disallows vertex shader texture sampling. See bugs 16157, 13838.
2008-06-26intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing.Eric Anholt
Most of these were to ensure that caches got synchronized between 2d (or meta) rendering and later use of the target as a source, such as for texture miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(), which just drops an MI_FLUSH. Most of the remainder were to ensure that REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped. Those are now replaced by automatically flushing those when dropping the lock.
2008-06-24Merge commit 'origin/master' into drm-gemEric Anholt
2008-06-24i965: Use the shared intel_pixel_copy.c.Eric Anholt
This disables the textured copy implementation on 965, which didn't appear to work (mesa copypix demo, disable the blit path, move so that regions don't overlap and textured is used, and you get garbage). If we resurrect this for i965, I'd rather it used the 915-style metaops instead. Current metaops code left in place so that whoever picks it up has a reference.
2008-06-24intel: Same pixel function init for everyone now.Eric Anholt
2008-06-24intel: Avoid glBitmap software fallback for blending when no blending occurs.Eric Anholt
Mesa demos tend to leave blending on but in GL_ONE/GL_ZERO, or GL_SRC_ALPHA/GL_ONE_MINUS_SRC_ALPHA with a source alpha of 1.0.
2008-06-24intel: Merge check_blit_fragment_ops between i915/i965.Eric Anholt
Both had some useful bits for the other.
2008-06-21replace __inline and __inline__ with INLINE macroBrian Paul
2008-06-18Merge commit 'origin/master' into drm-gemEric Anholt
2008-06-11[intel-gem] Chase domain flag renaming in the DRM.Eric Anholt
This is an API breakage only.
2008-06-10i965: apply commit 6c1a98e97affb2163e776551eb3a9e669ff99bbf to glslXiang, Haihao
2008-06-08i965: fix OPCODE_TEX when additional ops are neededRoland Scheidegger
2008-06-03Merge commit 'origin/master' into drm-gemKeith Packard
Conflicts: src/mesa/drivers/dri/common/dri_bufmgr.h src/mesa/drivers/dri/intel/intel_bufmgr_ttm.c src/mesa/drivers/dri/intel/intel_bufmgr_ttm.h src/mesa/drivers/dri/intel/intel_ioctl.c
2008-06-03[intel] Convert drivers to using libdrm bufmgr code.Eric Anholt
2008-05-23Emit a flush after the swapbuffers blit, so contents end up on the screen.Eric Anholt
Otherwise, since the MI_FLUSH at the end of every batch had been removed, non-automatic-flushing chips (965) wouldn't get flushed and apps with static rendering would get partial screen contents until the server's blockhandler flush kicked in.
2008-05-20i965: Check fallback before accounting for index/vertex buffer size. fix #16028.Xiang, Haihao
2008-05-07GEM: Remove already-disabled PIPE_CONTROL command.Eric Anholt
This existed to get the icache flushed. However, GEM handles this for us now for sure, and we had disabled it prematurely anyway.
2008-05-07GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.Eric Anholt
The GEM flags are much more descriptive for what we need. Since this makes bufmgr_fake rather device-specific, move it to the intel common directory. We've wanted to do device-specific stuff to it before.
2008-05-06i965: fix googleearth in classic mode.Dave Airlie
In classic mode googleearth triggered a case where vbos weren't getting accounted properly.
2008-05-05i965: Don't cast the result of brw_prepare_vertices to an unsigned value.Xiang, Haihao
Negative value means other errors, not aperture overflow. fix bug #15752
2008-05-02Add intel_bufmgr_gem for new graphics execution manager.Eric Anholt
2008-05-02[intel] Warnings fixes.Eric Anholt
2008-05-02[intel] Merge intel_ioctl.h. Not sure how this slipped by in the .c merge.Eric Anholt
2008-04-25[i965] short immediate values must be replicated to both halves of the dwordKeith Packard
The 32-bit immediate value in the i965 instruction word must contain two copies of any 16-bit constants. brw_imm_uw and brw_imm_w just needed to copy the value into both halves of the immediate value instruction field.
2008-04-22i965: fix DEPTH_TEXTURE_MODE (bug #14220)Xiang, Haihao
2008-04-22 [i965] This is to fix random crash in some maps of Ut2004 demo.Zou Nan hai
e.g. bridge of fate. If vs output is big, driver may fall back to use 8 urb entries for vs, unfortunally, for some unknown reason, if vs is working at 4x2 mode, 8 entries is not enough, may lead to gpu hang.
2008-04-18i965: fixup depth buffer checkDave Airlie
2008-04-18i965: fix vb aperture space checkDave Airlie
2008-04-18965: fix vb upload size checkDave Airlie
2008-04-18i965: fix gs_prog aperture checkDave Airlie
2008-04-18i965: initial attempt at fixing the aperture overflowDave Airlie
Makes state emission into a 2 phase, prepare sets things up and accounts the size of all referenced buffer objects. The emit stage then actually does the batchbuffer touching for emitting the objects. There is an assert in dri_emit_reloc if a reloc occurs for a buffer that hasn't been accounted yet.
2008-04-17Revert "[i965] renable regative rhw test"Xiang, Haihao
This reverts commit 3158e981f5f37768e9b04765704b9eaece8b899b. rhw issue has gone away on IGD.
2008-03-28i965: depth offset on glPolygonMode(GL_LINE/GL_POINT)Xiang, Haihao
2008-03-26[965] Fix massively broken state cache dirty flagging.Michal Wajdeczko
It was flagging a last_bo update even when last_bo didn't change, but another part was failing to update last_bo when it should have.
2008-03-26[965] Don't let the negate flags of src0 affect 1 constants in precalc_dst/litEric Anholt
This patch is a variant of a submission by Michal Wajdeczko to fix oglconform fpalu failures.
2008-03-26[965] Correctly set read mask for OPCODE_SWZ in pass1.Michal Wajdeczko
While OPCODE_SWZ has usually been optimized away in pass0, it may still exist if a SWZ with dst saturate was emitted in pass_fp. Fixes an error in oglconform fpalu.c.
2008-03-26[965] Clean up whitespace and dead code from do_unfilled change.Eric Anholt
2008-03-21[965] Avoid emitting dead code for DPx/math instructions.Michal Wajdeczko
The pass1 optimization stage clears out writemasks and registers, but the instructions themselves are still being processed at this stage, and could have resulted in them still being emitted.
2008-03-21[965] Improve pinterp performance by delaying reads of just-written regs.Michal Wajdeczko
2008-03-21[965] Fix negating of unsigned value in emit_wpos_xy.Michal Wajdeczko
2008-03-21[965] Add MVP code for position invariant vertex programs.Michal Wajdeczko
This fixes the arbvptorus demo.
2008-03-21[965] Shuffle state flags to match the order we initialize them in.Michal Wajdeczko
2008-03-21 [i965] multiple rendering target fixZou Nan hai
2008-03-19[965] Initialize region surface key structure padding.Eric Anholt
Fixes valgrind warnings, and potential performance loss from cache misses.
2008-03-18Revert "[i965] make stipple pattern continue across GL_LINE_LOOP and ↵Zou Nan hai
GL_LINE_STRIP" There is no information in GS to determinate when to reset line stipple count, still fallback to software This reverts commit 5a0314b431ab147c6156c3011f4cb54161ba4b25.
2008-03-18[i965] make stipple pattern continue across GL_LINE_LOOP and GL_LINE_STRIPZou Nan hai
2008-03-17[965] Fix fp temp reg release code to not usually release all temps.Andrzej Trznadel
Also, use wrapped ffs() instead of native.
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