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state."
I had forgotten part of brw_state_cache.c that made this fix not relevant for
master (last_addr comparison and flagging based on cache id).
This reverts commit a4642f3d18bdaebaba31e5dee72fe5de9d890ffb.
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Otherwise, choosing a new program wouldn't necessarily update the state, and
and an old program could be executed, leading to various sorts of pretty
pictures or hangs.
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Reduces diff to branch which has a relocation in this state emit.
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it should be handled in fb_write.
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Pixel Mask Copy is modified as the pixel shader thread
turns off pixels based on kill instructions.
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It makes quake4-demo works well on 965.
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to IP pre-increment, and should point to
the first instruction after the do instruction
of the do-while block of code
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The only functional difference should be that 965 now gets the optimization
where textures default to 16bpp when the screen is 16bpp.
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* Fix crash at context creation in most drivers supporting vblank.
* Don't pass vblank sequence or flags to functions that get passed the drawable
private already.
* Attempt to initialize vblank related drawable private fields just once
per drawable. May need more work in some drivers.
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Consolidate support for synchronizing to and retrieving vblank counters. Also
fix the core vblank code to return monotonic MSC counters, which are required
by some GLX extensions. Adding support for multiple pipes to a low level
driver is fairly easy, the Intel 965 driver provides simple example code (see
intel_buffers.c:intelWindowMoved()).
The new code bumps the media stream counter extension version to 2 and adds a
new getDrawableMSC callback. This callback takes a drawablePrivate pointer,
which is used to calculate the MSC value seen by clients based on the actual
vblank counter(s) returned from the kernel. The new drawable private fields
are as follows:
- vblSeq - used for tracking vblank counts for buffer swapping
- vblFlags - flags (e.g. current pipe), updated by low level driver
- msc_base - MSC counter from the last time the current pipe changed
- vblank_base - kernel DRM vblank counter from the last time the pipe changed
Using the above variables, the core vblank code (in vblank.c) can calculate a
monotonic MSC value. The low level DRI drivers are responsible for updating
the current pipe (by setting VBLANK_FLAG_SECONDARY for example in vblFlags)
along with msc_base and vblank_base whenever the pipe associated with a given
drawable changes (again, see intelWindowMoved for an example of this).
Drivers should fill in the GetDrawableMSC DriverAPIRec field to point to
driDrawableGetMSC32 and add code for pipe switching as outlined above to fully
support the new scheme.
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Conflicts:
src/mesa/drivers/dri/i965/brw_sf.h
src/mesa/drivers/dri/i965/intel_context.c
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Conflicts:
src/mesa/drivers/dri/i915/intel_screen.c
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This pulls the top level createNewScreen entry point out of the drivers
and rewrites __driUtilCreateNewScreen in dri_util.c to be the new entry point.
The change moves more logic into the common/ layer and changes the
createNewScreen entry point to only be defined in one place.
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The screenConfigs field of __DRIscreen points back to the containing
__GLXscreenConfigs struct. This is a serious abstraction violation; it
assumes that the loader is libGL and that there *is* a __GLXscreenConfigs
type in the loader.
Using the containerOf macro, we can get from the __DRIscreen pointer to
the containing __GLXscreenConfigs struct, at a place in the stack
where the above is a valid assumption. Besides, the __DRI* structs shouldn't
hold state other than the private pointer.
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Many DRI entry points took a __DRInativeDisplay pointer and a screen
index as arguments. The only use for the native display pointer was to
pass it back to the loader when looking up the __DRIscreen for the given
screen index.
Instead, let's just pass in the __DRIscreen pointer directly, which
let's drop the __DRInativeDisplay type and the getScreen function.
The assumption is now that the loader will be able to retrieve context
from the __DRIscreen pointer when necessary.
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1. spec requite result (0, 0, 0, 1) instead of (0, 0, 0, 0)
2. support shadow sampler in simd8
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In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
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This is in preparation for 965 TTM.
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OUT_BATCH is far more amenable to the upcoming relocations being done for TTM
support.
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This reverts commit b2f1aa2389473ed09170713301b042661d70a48e.
Somehow I ended up with my branch's save-this-while-I-work-on-master commit
actually on master.
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This code existed to dump logs of hardware access to be replayed in simulation.
Since we have real hardware now, it's not really needed.
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