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path: root/src/mesa/drivers/dri/i965
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2009-09-09Merge branch 'mesa_7_6_branch'Brian Paul
2009-09-09Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul
Conflicts: Makefile configs/default progs/glsl/Makefile src/gallium/auxiliary/util/u_simple_shaders.c src/gallium/state_trackers/glx/xlib/xm_api.c src/mesa/drivers/dri/i965/brw_draw_upload.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/intel/intel_context.h src/mesa/drivers/dri/intel/intel_pixel.c src/mesa/drivers/dri/intel/intel_pixel_read.c src/mesa/main/texenvprogram.c src/mesa/main/version.h
2009-09-08intel: Add support for ARB_draw_elements_base_vertex.Eric Anholt
On the 965, we just drop the value into the primitive packet. On non-945, we rely on the sw tnl code handling it.
2009-09-08i965: Add support for ARB_depth_clamp.Eric Anholt
2009-09-08i965: Respect spec requirement for pixel shader computed depth with no zbuffer.Eric Anholt
2009-09-08i965: Set NULL WM surfaces as tiled according to requirement by specs.Eric Anholt
2009-09-08i965: Use the renderbuffer surface size instead of region size for WM surfaces.Eric Anholt
For drawing to lower mipmap levels, the region size makes the renderbuffer be the size of the lowest level, instead of the current level. On DRI1, Brian previously found that the RB size was incorrect, so leave this broken there.
2009-09-08i965: #include clean-upsBrian Paul
2009-09-08i965: use _mesa_is_bufferobj()Brian Paul
2009-09-08i965: fix incorrect test for vertex position attributeBrian Paul
2009-09-04intel: Also get the DRI2 front buffer when doing front buffer reading.Eric Anholt
(cherry picked from commit df70d3049a396af3601d2a1747770635a74120bb)
2009-09-04intel: Update Mesa state before span setup in glReadPixels.Eric Anholt
We could have mapped the wrong set of draw buffers. Noticed while looking into a DRI2 glean ReadPixels issue. (cherry picked from commit afc981ee46791838f3cb83e11eb33938aa3efc83)
2009-09-04i965: Don't set the complete field when there is more VUE yet to come.Eric Anholt
This should help with things like lightsmark, but I don't have a testcase for this commit.
2009-09-04i965: Add support for 2 threads in the GS.Eric Anholt
This brings noop vertex shader throughput from 6.8M verts/sec to 10.4M verts/sec using GL_QUADs on my GM45.
2009-09-04i965: Add support for KIL_NV in brw_wm_emit.cEric Anholt
I ran into this lack of support when writing a shader that always discarded the fragments.
2009-09-04i965: Add missing state dependency of sf_unit on _NEW_BUFFERS.Eric Anholt
(cherry picked from commit 99174e7630676307f618c252755a20ba61ad9158)
2009-09-04intel: Align cubemap texture height to its padding requirements.Eric Anholt
(cherry picked from commit a70e1315846cd5e8d6f2b622821ff8262fe7179d) (cherry picked from commit 29e51c3872531366570d032147abad50f8a3c1af)
2009-09-04i965: Fix source depth reg setting for FSes reading and writing to depth.Eric Anholt
For some IZ setups, we'd forget to account for the source depth register being present, so we'd both read the wrong reg, and write output depth to the wrong reg. Bug #22603. (cherry picked from commit f44916414ecd2b888c8a680d56b7467ccdff6886)
2009-09-04i965: Respect CondSwizzle in OPCODE_IF.Eric Anholt
Fixes piglit glsl-vs-if-bool and progs/glsl/twoside, and will likely be useful for the looping code. Bug #18992 (cherry picked from commit 78c022acd0b37bf8b32f04313d76255255e769c1) (cherry picked from commit 63d7a2f53fb38e170f4e55f2b599e918edf2c512)
2009-09-04i965: asst clean-ups, etc in brw_vs_emit()Brian Paul
(cherry picked from commit fd7d764514c540987549c3ea88a2d669b0f0ea58)
2009-09-04i965: Emit conditional code updates as required for GLSL VS if statements.Eric Anholt
Previously, we'd be branching based on whatever condition code happened to be laying around. (cherry picked from commit 7007f8b352763af89805f287153cb7972bff0523)
2009-09-04i965: Spell "conditional" correctly.Eric Anholt
2009-09-04i965: Fix RECT shadow sampling by not losing the other texcoords.Eric Anholt
Bug #20821 (cherry picked from commit 191e028de20b2f954621b652aa77b06d0e93652a)
2009-09-04i965: Assert that the offset in the VBO is below the VBO size.Eric Anholt
This avoids sending a bad buffer address to the GPU due to programmer error, and is permitted by the ARB_vbo spec. Note that we still have the opportunity to dereference past the end of the GPU, because we aren't clipping to a correct _MaxElement, but that appears to be harder than it should be. This gets us the 90% solution. Bug #19911. (cherry picked from commit d7430d942f6c7950a92367aeb13b80cf76ccad78)
2009-09-04i965: Even if no VS inputs are set, still load some amount of URB as required.Eric Anholt
See comment on Vertex URB Entry Read Length for VS_STATE. This, combined with the previous three commits, fixes #22945. (cherry picked from commit e340d4f9866db4bae391288e83a630a310b0dd2b)
2009-09-04i965: Make sure the VS URB size is big enough to fit a VF VUE.Eric Anholt
This fix is just from code and docs inspection, but it may fix hangs on some applications. (cherry picked from commit e93848e595176ae0bad3bfe64e0ca63fd089bb72)
2009-09-04i965: Don't emit bad packets when no VBs are referenced.Eric Anholt
It appears that sometimes Mesa (and I suppose a VS could as well) emits a program which references no vertex data, and thus we end up with nr_enabled == 0 even though some VBs are enabled. We'd end up emitting VB/VE packet headers of 0xffffffff in that case, leading to GPU hangs. Bug #22945 (wine with an uncompiled VS) (cherry picked from commit d1fbfd0f962347e4153db3852292d44de5aea863)
2009-09-04i965: Calculate enabled[] and nr_enabled once and re-use the values.Eric Anholt
The code duplication bothered me. (cherry picked from commit 9b9cb30d128fc5f1ba77287696ecd508e640efde)
2009-09-04i965: Set the max index buffer address correctly according to the docs.Eric Anholt
It's the last addressable byte, not the byte after the end of the buffer. (cherry picked from commit b72dea5441e8e9226dabf1826fa3bc129c7bc281)
2009-09-04i965: rename var: s/tmp/vs_inputs/Brian Paul
(cherry picked from commit 840c09fc71542fdfc71edd2a2802925d467567bb)
2009-09-03intel: Add support for ARB_sync.Eric Anholt
We currently weasel out of supporting the timeout parameter, but otherwise this extension looks ready, and should make the common case happy.
2009-09-02Revert "i965: Use VBOs in the VBO module on 965, now that we have ↵Eric Anholt
ARB_map_buffer_range." This reverts commit 00413d87426f14df47d90ba3c995e1889e9f88ca. Even with fixes, using ARB_map_buffer_range in the VBO module isn't showing up as a significant win, and some cases apparently regressed. Bug #23624.
2009-09-02i965: CS FENCE in URB_FENCE is 11-bits wideXiang, Haihao
2009-09-02i965: validate sf stateXiang, Haihao
2009-08-29i965: Fix segfault with ARB_oq CheckQuery when results are already fetched.Eric Anholt
2009-08-29i965: Support PROGRAM_ENV_PARAMs in brw_vs_emit.cEric Anholt
2009-08-28i965: Use VBOs in the VBO module on 965, now that we have ARB_map_buffer_range.Eric Anholt
This looks like it's a small win on blender.
2009-08-28i965: Implement ARB_oq CheckQuery in the intended way.Eric Anholt
Previously we blocked because I hadn't added the libdrm function. Now it's there, so update your libdrm.
2009-08-26i965: Increase assmebly shader program parameter limitsIan Romanick
Increase the number of native program parameters to the same values exposed by GLSL.
2009-08-26ARB prog: Change handling of program parameter limitsIan Romanick
Several changes are made to program parameter limits. Several of the non-NATIVE limits are set higher. All of the NATIVE limits are set to zero in the core Mesa code. Each driver must set the actual value in its context creation routine. If the NATIVE value remains zero, this indicates that hardware shaders may not be supported. Each of the preceeding changes matches the bahavior of Apple's shader assembler, so it seems safe. Finally, we limit the value of MaxEnvParams to be no greater than MaxNativeAttribs. At least one case has been found where an application does the wrong thing if MaxNativeAttribs < MaxEnvParams. See also bugzilla #23490.
2009-08-26i965: init the tex_units_used fieldBrian Paul
2009-08-26i965: fix incorrect tex unit in emit_tex() and emit_txb()Brian Paul
The instructions we're translating already went through the brw_wm_pass_fp() function which does the sampler->texture unit mapping. We were applying the sample->unit mapping a second time in the GLSL texture emitters. Often, this made no difference but other times it could lead to accessing an invalid texture and could cause a GPU lockup.
2009-08-26i965: clean-up tex target switchesBrian Paul
2009-08-26i965: added texture unit sanity checkBrian Paul
Check that all the textures needed by the current fragment program actually exist and are valid.
2009-08-26i965: keep track of which texture units the fragment shader accessesBrian Paul
We'll use this for debug/sanity checking.
2009-08-26i965: clean up texture target switchesBrian Paul
2009-08-25i965: add some texture unit/target assertionsBrian Paul
2009-08-22i965: Implement frag prog DPH like DP4Ian Romanick
DPH can output to any component, not just to X. This allows fpalu.c to run without hitting the assertion in emit_dph.
2009-08-19intel: Fix failure to commit -a --amend before last push.Eric Anholt
2009-08-19intel: Align cubemap texture height to its padding requirements.Eric Anholt
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