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path: root/src/mesa/drivers/dri/i965
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2010-11-19i965: Recognize saturates and turn them into a saturated mov.Eric Anholt
On pre-gen6, this turns 4 instructions into 1. We could still do better by folding the saturate into the instruction generating the value if nobody else uses it, but that should be a separate pass.
2010-11-19i965: Fold constants into the second arg of BRW_SEL as well.Eric Anholt
This hits a common case with min/max operations.
2010-11-19i965: Remove extra \n at the end of every instruction in INTEL_DEBUG=wm.Eric Anholt
2010-11-19i965: Just use memset() to clear most members in FS constructors.Eric Anholt
This should make it a lot harder to forget to zero things.
2010-11-19i965: Fix compute_to_mrf to not move a MRF write up into another live range.Eric Anholt
Fixes glsl-fs-copy-propagation-texcoords-1.
2010-11-19glsl: Combine many instruction lowering passes into one.Kenneth Graunke
This should save on the overhead of tree-walking and provide a convenient place to add more instruction lowering in the future. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
2010-11-19glsl: Add ir_quadop_vector expressionIan Romanick
The vector operator collects 2, 3, or 4 scalar components into a vector. Doing this has several advantages. First, it will make ud-chain tracking for components of vectors much easier. Second, a later optimization pass could collect scalars into vectors to allow generation of SWZ instructions (or similar as operands to other instructions on R200 and i915). It also enables an easy way to generate IR for SWZ instructions in the ARB_vertex_program assembler.
2010-11-19glsl: Eliminate assumptions about size of ir_expression::operandsIan Romanick
This may grow in the near future.
2010-11-19glsl: Add ir_unop_sin_reduced and ir_unop_cos_reducedIan Romanick
The operate just like ir_unop_sin and ir_unop_cos except that they expect their inputs to be limited to the range [-pi, pi]. Several GPUs require this limited range for their sine and cosine instructions, so having these as operations (along with a to-be-written lowering pass) helps this architectures. These new operations also matche the semantics of the GL_ARB_fragment_program SCS instruction. Having these as operations helps in generating GLSL IR directly from assembly fragment programs.
2010-11-18i965: Eliminate dead code more aggressively.Eric Anholt
If an instruction writes reg but nothing later uses it, then we don't need to bother doing it. Before, we were just killing code that was never read after it was ever written. This removes many interpolation instructions for attributes with only a few comopnents used. Improves nexuiz high-settings performance .46% +/- .12% (n=3) on my Ironlake.
2010-11-18i965: Fail on loops on gen6 for now until we write the EU emit code for it.Eric Anholt
2010-11-18i965: Add dumping of the sampler default color.Eric Anholt
2010-11-18i965: Add state dumping for sampler state.Eric Anholt
2010-11-18i965: Shut up spurious gcc warning about GLSL_TYPE enums.Eric Anholt
2010-11-17glsl: Remove the ir_binop_cross opcode.Kenneth Graunke
2010-11-14i965: Fix gl_FragCoord inversion when drawing to an FBO.Eric Anholt
This showed up as cairo-gl gradients being inverted on everyone but Intel, where I'd apparently tweaked the transformation to work around the bug. Fixes piglit fbo-fragcoord.
2010-11-13i965: Silence uninitialized variable warning.Vinson Lee
Silences this GCC warning. brw_fs.cpp: In member function 'void fs_visitor::split_virtual_grfs()': brw_fs.cpp:2516: warning: unused variable 'reg'
2010-11-10i965: re-enable gen6 IF statements in the fragment shader.Eric Anholt
IF statements were getting flattened while they were broken. With Zhenyu's last fix for ENDIF's type, everything appears to have lined up to actually work. This regresses two tests: glsl1-! (not) operator (1, fail) glsl1-! (not) operator (1, pass) but fixes tests that couldn't work before because the IFs couldn't be flattened: glsl-fs-discard-01 occlusion-query-discard (and, naturally, this should be a performance improvement for apps that actually use IF statements to avoid executing a bunch of code).
2010-11-10i965: Work around strangeness in swizzling/masking of gen6 math.Eric Anholt
Sometimes we swizzled in a different channel it looked like, and sometimes we swizzled in zero. Or something. Having looked at the output of another code generator for this chip, this is approximately what they do, too: use align1 math on temporaries, and then move the results into place. Fixes: glean/vp1-EX2 test glean/vp1-EXP test glean/vp1-LG2 test glean/vp1-RCP test (reciprocal) glean/vp1-RSQ test 1 (reciprocal square root) shaders/glsl-cos shaders/glsl-sin shaders/glsl-vs-masked-cos shaders/vpfp-generic/vp-exp-alias
2010-11-10Revert "i965: VS use SPF mode on sandybridge for now"Zhenyu Wang
This reverts commit 9c39a9fcb2c76897e9b5aff68ce197a411c4e25c. Remove VS SPF mode, conditional instruction works for VS now.
2010-11-10i965: fix dest type of 'endif' on sandybridgeZhenyu Wang
That should also be immediate value for type W.
2010-11-09i965: Add support for math on constants in gen6 brw_wm_glsl.c path.Eric Anholt
Fixes 10 piglit cases that were assertion failing.
2010-11-09i965: Allow OPCODE_SWZ to put immediates in the first arg.Eric Anholt
Fixes assertion failure with texture swizzling in the GLSL path when it's triggered (such as gen6 FF or ARB_fp shadow comparisons). Fixes: texdepth texSwizzle fp1-DST test fp1-LIT test 3
2010-11-04i965: Silence uninitialized variable warning.Vinson Lee
Silences this GCC warning. brw_wm_fp.c: In function 'brw_wm_pass_fp': brw_wm_fp.c:966: warning: 'last_inst' may be used uninitialized in this function brw_wm_fp.c:966: note: 'last_inst' was declared here
2010-11-04i965: Silence uninitialized variable warning.Vinson Lee
Silences this GCC warning. brw_wm_fp.c: In function 'precalc_tex': brw_wm_fp.c:666: warning: 'tmpcoord.Index' may be used uninitialized in this function
2010-11-03i965: Remove dead intel_structs.h file.Eric Anholt
2010-11-03intel: Annotate debug printout checks with unlikely().Eric Anholt
This provides the optimizer with hints about code hotness, which we're quite certain about for debug printouts (or, rather, while we developers often hit the checks for debug printouts, we don't care about performance while doing so).
2010-11-02i965: refresh wm push constant also for BRW_NEW_FRAMENT_PROGRAM on gen6Zhenyu Wang
Fix compiz crash. https://bugs.freedesktop.org/show_bug.cgi?id=31124
2010-10-28i965: Update the gen6 stencil ref state when stencil state changes.Eric Anholt
Fixes 6 piglit tests about stencil operations.
2010-10-28i965: Upload required gen6 VS push constants even when using pull constants.Eric Anholt
Matches pre-gen6, and fixes glsl-vs-large-uniform-array.
2010-10-28i965: Update gen6 SF state when point state (sprite or attenuation) changes.Eric Anholt
2010-10-28i965: Add user clip planes support to gen6.Eric Anholt
Fixes piglit user-clip, and compiz desktop switching when dragging a window and using just 2 desktops. Bug #30446.
2010-10-27i965: Add bit operation support to the fragment shader backend.Kenneth Graunke
2010-10-27i965: Make FS uniforms be the actual type of the uniform at upload time.Eric Anholt
This fixes some insanity that would otherwise be required for GLSL 1.30 bit ops or gen6 integer uniform operations in general, at the cost of upload-time pain. Given that we only have that pain because mesa's mangling our integer uniforms to be floats, this something that should be fixed outside of the shader codegen.
2010-10-27Track separate programs for each stageIan Romanick
The assumption is that all stages are the same program or that varyings are passed between stages using built-in varyings.
2010-10-26i965: Disable register spilling on gen6 until it's fixed.Eric Anholt
Avoids GPU hang on glsl-fs-convolution-1.
2010-10-26i965: Fix VS URB entry sizing.Eric Anholt
I'm trying to clamp to a minimum of 1 URB row, not a maximum of 1. Fixes: glsl-kwin-blur glsl-max-varying glsl-routing
2010-10-26i965: Drop the eot argument to read messages, which can never be set.Eric Anholt
2010-10-26i965: Add support for constant buffer loads on gen6.Eric Anholt
Fixes glsl-fs-uniform-array-5.
2010-10-26i965: Set up the constant buffer on gen6 when it's needed.Eric Anholt
This was slightly confused because gen6_wm_constants does the push constant buffer, while brw_wm_constants does pull constants.
2010-10-26i965: Fix typo in comment about state flags.Eric Anholt
2010-10-26i965: Handle new ir_unop_round_even in channel expression splitting.Eric Anholt
2010-10-26i965: Add support for discard instructions on gen6.Eric Anholt
It's a little more painful than before because we don't have the handy mask register any more, and have to make do with cooking up a value out of the flag register.
2010-10-26i965: Add disasm for the flag register.Eric Anholt
2010-10-26i965: Clear some undefined fields of g0 when using them for gen6 FB writes.Eric Anholt
This doesn't appear to help any testcases I'm looking at, but it looks like it's required.
2010-10-26i965: Use SENDC on the first render target write on gen6.Eric Anholt
This is apparently required, as the thread will be initiated while it still has dependencies, and this is what waits for those to be resolved before writing color.
2010-10-26i965: Clarify an XXX comment in FB writes with real info.Eric Anholt
2010-10-26i965: Add EU code for dword scattered reads (constant buffer array indexing).Eric Anholt
2010-10-22i965: Add support for pull constants to the new FS backend.Eric Anholt
Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22i965: Move the FS disasm/annotation printout to codegen time.Eric Anholt
This makes it a lot easier to track down where we failed when some code emit triggers an assert. Plus, less memory allocation for codegen.