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path: root/src/mesa/drivers/dri/i965
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2010-10-26i965: Add EU code for dword scattered reads (constant buffer array indexing).Eric Anholt
2010-10-22i965: Add support for pull constants to the new FS backend.Eric Anholt
Fixes glsl-fs-uniform-array-5, but not 6 which fails in ir_to_mesa.
2010-10-22i965: Move the FS disasm/annotation printout to codegen time.Eric Anholt
This makes it a lot easier to track down where we failed when some code emit triggers an assert. Plus, less memory allocation for codegen.
2010-10-21i965: Be more aggressive in tracking live/dead intervals within loops.Eric Anholt
Fixes glsl-fs-convolution-2, which was blowing up due to the array access insanity getting at the uniform values within the loop. Each temporary was considered live across the whole loop.
2010-10-21i965: Correct scratch space allocation.Eric Anholt
One, it was allocating increments of 1kb, but per thread scratch space is a power of two. Two, the new FS wasn't getting total_scratch set at all, so everyone thought they had 1kb and writes beyond 1kb would go stomping on a neighbor thread. With this plus the previous register spilling for the new FS, glsl-fs-convolution-1 passes.
2010-10-21i965: Don't emit register spill offsets directly into g0.Eric Anholt
g0 is used by others, and is expected to be left exactly as it was dispatched to us. So manually move g0 into our message reg when spilling/unspilling and update the offset in the MRF. Fixes failures in texture sampling after having spilled a register.
2010-10-21i965: Add support for register spilling.Eric Anholt
It can be tested with if (0) replaced with if (1) to force spilling for all virtual GRFs. Some simple tests work, but large texturing tests fail.
2010-10-21i965: Fix gl_FrontFacing emit on pre-gen6.Eric Anholt
It's amazing this code worked. Basically, we would get lucky in register allocation and the tests using frontfacing would happen to allocate gl_FrontFacing storage and the instructions generating gl_FrontFacing but pointing at another register to the same hardware register. Noticed during register spilling debug, when suddenly they didn't get allocatd the same storage.
2010-10-21i965: Split register allocation out of the ever-growing brw_fs.cpp.Eric Anholt
2010-10-19i965: Use the new style of IF statement with embedded comparison on gen6.Eric Anholt
"Everyone else" does it this way, so follow suit. It's fewer instructions, anyway.
2010-10-19i965: Set the source operand types for gen6 if/else/endif to integer.Eric Anholt
I don't think this should matter, but I'm not sure, and it's recommended by a kernel checker in fulsim.
2010-10-19i965: Add EU emit support for gen6's new IF instruction with comparison.Eric Anholt
2010-10-19i965: Disable thread dispatch when the FS doesn't do any work.Eric Anholt
This should reduce the cost of generating shadow maps, for example. No performance difference measured in nexuiz, though it does trigger this path.
2010-10-19i965: Remove the gen6 emit_mi_flushes I sprinkled around the driver.Eric Anholt
These were for debugging in bringup. Now that relatively complicated apps are working, they haven't helped debug anything in quite a while.
2010-10-19i965: Tell the shader compiler when we expect depth writes for gen6.Eric Anholt
This fixes hangs in some Z-writes-in-shaders tests, though other pieces don't come out correctly. Bug #30392: hang in fbo-fblit-d24s8. (still fails with bad color drawn to some targets)
2010-10-18i965: Remove unused variable.Kenneth Graunke
2010-10-18i965: Fix scissor-offscreen on gen6 like we did pre-gen6.Eric Anholt
2010-10-18i965: Assert out on gen6 VS constant buffer reads that hang the GPU for now.Eric Anholt
2010-10-18i965: Fix a weirdness in NOT handling.Eric Anholt
XOR makes much more sense. Note that the previous code would have failed for not(not(x)), but that gets optimized out.
2010-10-18i965: Disable the debug printf I added for FS disasm.Eric Anholt
2010-10-18i965: Add missing "break" statement.Kenneth Graunke
Otherwise, it would try to handle arrays as structures, use uninitialized memory, and crash.
2010-10-15i965: Set the type of the null register to fix gen6 FS comparisons.Eric Anholt
We often use reg_null as the destination when setting up the flag regs. However, on gen6 there aren't general implicit conversions to destination types from src types, so the comparison to produce the flag regs would be done on the integer result interpreted as a float. Hilarity ensued. Fixes 20 piglit cases.
2010-10-15i965: Fix indentation after commit 3322fbafIan Romanick
2010-10-14glsl: Slightly change the semantic of _LinkedShadersIan Romanick
Previously _LinkedShaders was a compact array of the linked shaders for each shader stage. Now it is arranged such that each slot, indexed by the MESA_SHADER_* defines, refers to a specific shader stage. As a result, some slots will be NULL. This makes things a little more complex in the linker, but it simplifies things in other places. As a side effect _NumLinkedShaders is removed. NOTE: This may be a candidate for the 7.9 branch. If there are other patches that get backported to 7.9 that use _LinkedShader, this patch should be cherry picked also.
2010-10-14i965: Fix texturing on pre-gen5.Eric Anholt
I broke it in 06fd639c519214b6ebcbf29127b6d9ed429f8641 by only testing 2 generations of hardware :(
2010-10-14i965: Add support for ir_unop_round_even via the RNDE instruction.Kenneth Graunke
2010-10-14i965: Clean up a warning in the old fragment backend.Kenneth Graunke
Hopefully this code can just go away soon.
2010-10-14i965: Enable the new FS backend on pre-gen6 as well.Eric Anholt
It is now to the point where we have no regressing piglit tests. It also fixes Yo Frankie! and Humus DynamicBranching, probably due to the piglit bias tests that work that didn't on the Mesa IR backend. As a downside, performance takes about a 5-10% performance hit at the moment (e.g. nexuiz 19.8fps -> 18.8fps), which I plan to resolve by reintroducing 16-wide fragment shaders where possible. It is a win, though, for fragment shaders using flow control.
2010-10-14i965: Correctly emit the RNDZ instruction.Kenneth Graunke
Simply using RNDU, RNDZ, or RNDE does not produce the desired result. Rather, the RND* instructions place a value in the destination register that may be 1 less than the correct answer. They can also set per-channel "increment bits" in a flag register, which, if set, mean dest needs to be incremented by 1. A second instruction - a predicated add - completes the job. Notably, RNDD always produces the correct answer in a single instruction. Fixes piglit test glsl-fs-trunc.
2010-10-14i965: Use RNDZ for ir_unop_trunc in the new FS.Kenneth Graunke
The existing code used RNDD, which rounds down, rather than toward zero.
2010-10-14i965: Use logical-not when emitting ir_unop_ceil.Kenneth Graunke
Fixes piglit test glsl-fs-ceil.
2010-10-14i965: Add peepholing of conditional mod generation from expressions.Eric Anholt
This cuts usually 2 out of 3 instructions for flag reg generation (if statements, conditional assignment) by producing the conditional mod in the expression representing the boolean value. Fixes glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined (register allocation no longer fails for the conditional generation proliferation)
2010-10-14i965: Add a function for handling the move of boolean values to flag regs.Eric Anholt
This will be a place to peephole comparisions directly to the flag regs, and for now avoids using MOV with conditional mod on gen6, which is now illegal.
2010-10-14i965: Add a pass to the FS to split virtual GRFs to float channels.Eric Anholt
Improves nexuiz performance 0.91% (+/- 0.54%, n=8)
2010-10-14i965: Update the live interval when coalescing regs.Eric Anholt
2010-10-14i965: Set class_sizes[] for the aligned reg pair class.Eric Anholt
So far, I've only seen this be a valgrind warning and not a real failure.
2010-10-14Revert "i965: fallback lineloop on sandybridge for now"Zhenyu Wang
This reverts commit 73dab75b4165f7d2214a68d4ba8e3cb7aab9b4ac.
2010-10-14i965: Fix GS hang on SandybridgeZhenyu Wang
Don't use r0 for FF_SYNC dest reg on Sandybridge, which would smash FFID field in GS payload, that cause later URB write fail. Also not use r0 in any URB write requiring allocate.
2010-10-13i965: Add support for rescaling GL_TEXTURE_RECTANGLE coords to new FS.Eric Anholt
2010-10-13Drop GLcontext typedef and use struct gl_context insteadKristian Høgsberg
2010-10-13Rename GLvisual and __GLcontextModes to struct gl_configKristian Høgsberg
2010-10-12i965: Don't rebase the index buffer to min 0 if any arrays are in VBOs.Eric Anholt
There was a check to only do the rebase if we didn't have everything in VBOs, but nexuiz apparently hands us a mix of VBOs and arrays, resulting in blocking on the GPU to do a rebase. Improves nexuiz 800x600, high-settings performance on my Ironlake 41% (+/- 1.3%), from 14.0fps to 19.7fps.
2010-10-12i965: Fix missing "break;" in i2b/f2b, and missing AND of CMP result.Eric Anholt
Fixes glsl-fs-i2b.
2010-10-11i965: Always use the new FS backend on gen6.Eric Anholt
It's now much more correct for gen6 than the old backend, with just 2 regressions I've found (one of which is common with pre-gen6 and will be fixed by an array splitting IR pass). This does leave the old Mesa IR backend getting used still when we don't have GLSL IR, but the plan is to get GLSL IR input to the driver for the ARB programs and fixed function by the next release.
2010-10-11i965: Fix gen6 pixel_[xy] setup to avoid mixing int and float src operands.Eric Anholt
Pre-gen6, you could mix int and float just fine. Now, you get goofy results. Fixes: glsl-arb-fragment-coord-conventions glsl-fs-fragcoord glsl-fs-if-greater glsl-fs-if-greater-equal glsl-fs-if-less glsl-fs-if-less-equal
2010-10-11i965: Don't compute-to-MRF in gen6 VS math.Eric Anholt
There was code to do this for pre-gen6 already, this just enables it for gen6 as well.
2010-10-11i965: Expand uniform args to gen6 math to full registers to get hstride == 1.Eric Anholt
This is a hw requirement in math args. This also is inefficient, as we're calculating the same result 8 times, but then we've been doing that on pre-gen6 as well. If we're doing math on uniforms, though, we'd probably be better served by having some sort of mechanism for precalculating those results into another uniform value to use. Fixes 7 piglit math tests.
2010-10-11i965: Don't compute-to-MRF in gen6 math instructions.Eric Anholt
2010-10-11i965: Add a couple of checks for gen6 math instruction limits.Eric Anholt
2010-10-11i965: Don't consider gen6 math instructions to write to MRFs.Eric Anholt
This was leftover from the pre-gen6 cleanups. One tests regresses where compute-to-MRF now occurs.