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path: root/src/mesa/drivers/dri/i965
AgeCommit message (Collapse)Author
2007-09-20i965: fix an error in brw_vs_tnl.cXiang, Haihao
if the state of TEXMAT is changed, the VS isn't updated.
2007-09-14i965: align the address of the first element withinXiang, Haihao
the index buffer. (fix#11910)
2007-09-12i965: translate shadow compare function into correctXiang, Haihao
internal function to match the EXT_shadow_funs spec. fix bug#11925
2007-09-12i965: revert commit 1a15b2169ba6cb100627eb525a20a00537cfb6f0,Xiang, Haihao
and keep the instruction state unchanged after calling brw_emit_tri_setup/brw_emit_line_setup when building setup thread for SF_UNFILLED_TRIS.
2007-09-11Fix-up #includes to remove some -I options.Brian
eg: #include "shader/program.h" and remove -I$(TOP)/src/mesa/program
2007-09-11i965: take the secondary color into account when drawingXiang, Haihao
bitmap. fix#10688
2007-09-11i965: limit on LOD Bias, fix#11987Xiang, Haihao
2007-09-05i965: only take non-varying attribute into account whenXiang, Haihao
compiling sf_prog. fix bug#11378 (which is introduced by commit d619cceea47dc3070ebb7f7ea4f8b6b31a672d38)
2007-09-01i965: Correct build_lighting in i965 driver according toXiang, Haihao
commit 6dd98e9853a6984150aa47467112e016c40a4ab4.
2007-08-31i965: Calculate the positional light in homogeneous coordinates.Xiang, Haihao
fix bug#11009
2007-08-31 optimize 965 clipZou Nan hai
1. increase clip thread number to 2 2. do cliptest for -rhw
2007-08-31i965: Take the upper limitation on LOD into account.Xiang, Haihao
2007-08-30Bug #10571: Fix 965 line clipping when neither vertex needs clipping.David Moore
2007-08-29i965: store read drawable info in intel_context. Some OpenGLXiang, Haihao
operations are based on read drawable. fix bug#10136.
2007-08-29i965: check NULL pointer. fix bug#12193Xiang, Haihao
2007-08-29i965: samplers group in fours in WM_STATE. fix bug#9415Xiang, Haihao
2007-08-28i965: flush batch buffer when getting the maximum. This makesXiang, Haihao
some 3D programs such as pymol work well.
2007-08-17i965: align width/height for volume textureXiang, Haihao
2007-08-15i965: use BRW_TEXCOORDMODE_CLAMP instead of BRW_TEXCOORDMODE_CLAMP_BORDERXiang, Haihao
to implement GL_CLAMP
2007-08-13i965: fix projtex_maskXiang, Haihao
projtex_mask is only an 8bit field, and wm.input_size_masks includes other attributes' information, therefore right shift is needed.
2007-08-10i965: roland's DXTn format texture patch(bug10347)Xiang, Haihao
2007-08-10i965/i915tex: applying right alignment to compressed texture,Xiang, Haihao
which make small textures(4x4,2x2,1x1) work well.
2007-08-10i965: set mt->cpp differently with compressed textureXiang, Haihao
2007-08-02Fix typo in logic for unalias2()Keith Whitwell
2007-08-02 fix fd.o bug #11804Zou Nan hai
glPolygonMode with point sprite on i965
2007-08-02 Fix previous commitZou Nan hai
2007-08-02 EXT_texture_sRGB support on i965Zou Nan hai
2007-08-01 fix fd.o bug #11788, max point sizeZou Nan hai
2007-07-31i965: fix bad casts in do_blit_bitmap to support WindowPos correctlyXiang, Haihao
2007-07-31i965: Use I16_UNORM instead of L16_UNORM (bug 11742)Xiang, Haihao
2007-07-30 ARB sprite point support on i965Zou Nan hai
2007-07-21Remove ctx->Point._Size and ctx->Line._Width.Brian
The clamping for these values depends on whether we're drawing AA or non-AA points, lines. Defer clamping until drawing time. Drivers could compute and keep clamped AA and clamped non-AA values if desired.
2007-07-04fix LogicOp/bitmap problem, bug 11133Eric Anholt
2007-06-11Replace texobj->Complete with texobj->_Complete since it's a derived field.Brian
2007-05-31i965: Add pci info for 965GME/GLE chip.Wang Zhenyu
2007-05-22Replace initInitState() with _mesa_init_driver_state().Brian
2007-05-22include swrast_setup/swrast_setup.h to silence warningBrian
2007-05-22fog: fix potential issues with generated vp using fogRoland Scheidegger
Change the generated vertex programs (tnl/brw) to follow the same logic as the tnl fog wrt using absolute value, and sync them up a bit (untested).
2007-05-03add some #includes to silence warningsBrian
2007-03-30Merge branch 'crestline-qa', adding support for the 965GM chipset.Eric Anholt
2007-03-27 Fix compile errorZou Nan hai
2007-03-26merge of glsl-compiler-1 branchBrian
2007-03-26Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2007-03-25i965: The given urb layout(maximal size of urb entries and theXiang, Haihao
values for nr of entries) should meet the requirement.
2007-03-22Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2007-03-22fix for bug#10339Xiang, Haihao
StateFlags has been updated in _mesa_add_state_reference
2007-03-21merge from masterBrian
2007-03-21fix copy and paste bug from last commit in fog generation code for GL_LINEAR fogRoland Scheidegger
2007-03-21Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestlineNian Wu
2007-03-20fix for bug#10347Xiang, Haihao
not sure which brw surface for DXT3 & DXT5, so restore the previous choice.(changed in commit 84081774e62a8af18e6bf894ea69f63b97dcfe96)
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