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path: root/src/mesa/drivers/dri/i965
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2009-04-14i965: fix VS constant buffer readsBrian Paul
This mostly came down to finding the right MRF incantation in the brw_dp_READ_4_vs() function. Note: this feature is still disabled (but getting close to done).
2009-04-14i965: checkpoint commit: VS constant buffersBrian Paul
Hook up a constant buffer, binding table, etc for the VS unit. This will allow using large constant buffers with vertex shaders. The new code is disabled at this time (use_const_buffer=FALSE).
2009-04-10i965: remove unused varBrian Paul
2009-04-10i965: clean-up in prepare_wm_surfaces()Brian Paul
2009-04-10i965: added null const_buffer pointer check in update_constant_buffer()Brian Paul
2009-04-09i965: re-org of some of the new constant buffer codeBrian Paul
Plus, begin the new code for vertex shader const buffers.
2009-04-09i965: new SURF_INDEX_ macrosBrian Paul
Used to map drawables, textures and constant buffers to surface binding table indexes.
2009-04-09i965: free shader's constant buffer in brwDeleteProgram()Brian Paul
Fixes mem leak observed with texcombine test.
2009-04-08i965: set BRW_MASK_DISABLE flag in "send" instruction in brw_dp_READ_4()Brian Paul
This fixes the random results that were seen when fetching a constant inside an IF/ELSE clause. Disabling the execution mask ensures that all the components of the register are written.
2009-04-08i965: clean-ups, debug code in brw_wm_glsl.cBrian Paul
2009-04-08i965: init current_const[i].index = -1Brian Paul
2009-04-08i965: move the fetch_constants() call before setting conditional mod stateBrian Paul
Before, the instruction's CondUpdate field was mistakenly effecting the constant-fetch operation. Fixes progs/glsl/bump.c demo. But there are some other issues related to condition flags and IF/ELSE that need investigation...
2009-04-06i965: Use GTT maps when available to upload vertex arrays and system VBOs.Eric Anholt
This speeds up OA on my GM45 by 21% (more than the original CPU cost of the upload path). We might still be able to squeeze a few more percent out by avoiding repeatedly mapping/unmapping buffers as we upload elements into them.
2009-04-03i965: remove unused varBrian Paul
2009-04-03i965: more const buffer debug codeBrian Paul
2009-04-03i965: added brw_same_reg()Brian Paul
2009-04-03i965: s/GL_FALSE/BRW_COMPRESSION_NONE/Brian Paul
2009-04-03i965: another checkpoint commit of new constant buffer supportBrian Paul
Everything is in place now for using a true constant buffer for GLSL fragment shaders. Still some bugs to find though.
2009-04-03i965: fix response length param in brw_dp_READ_4()Brian Paul
We were accidentally clobbering the next register.
2009-04-03i965: change args to get_src_reg() to prep for new constant buffer supportBrian Paul
2009-04-03i965: check-point commit of new constant buffer supportBrian Paul
Currently, shader constants are stored in the GRF (loaded from the CURBE prior to shader execution). This severly limits the number of constants and temps that we can support. This new code will support (practically) unlimited size constant buffers and free up registers in the GRF. We allocate a new buffer object for the constants and read them with "Read" messages/instructions. When only a small number of constants are used, we can still use the old method. The code works for fragment shaders only (and is actually disabled) for now. Need to do the same thing for vertex shaders and need to add the necessary code-gen to fetch the constants which are referenced by the shader instructions.
2009-04-03i965: remove unused code for sampling a constant bufferBrian Paul
2009-04-03i965: code to setup a constant buffer samplerBrian Paul
This code won't actually be used and will be removed in a subsequent commit. Just committing for posterity.
2009-04-03i965: do negation and Abs in get_src_reg_imm()Brian Paul
Fixes regression seen with progs/glsl/bump.c
2009-04-03i965: commentsBrian Paul
2009-04-03i965: code to debug/dump instruction immediatesBrian Paul
2009-04-03i965: minor code movement, new commentBrian Paul
2009-04-03i965: added new brw_dp_READ_4() functionBrian Paul
Used to read float[4] vectors from the constant buffer/surface.
2009-04-03i965: new and updated commentsBrian Paul
2009-04-03i965: comments for brw_SAMPLE()Brian Paul
2009-04-03i965: comments for sampling codeBrian Paul
2009-04-03i965: add support for float literal instruction operandsBrian Paul
Call the get_src_reg_imm() function when it's permissible to generate a literal value src register.
2009-04-03i965: remove 'nr' param from get_src/dst_reg() functionsBrian Paul
The value was always 1.
2009-04-03i965: fix comment typoBrian Paul
2009-04-03i965: comments, clean-up in prepare_wm_surfaces()Brian Paul
2009-04-03i965: remove unneeded #includesBrian Paul
2009-04-03i965: formatting clean-upsBrian Paul
2009-04-03i965: comments, whitespace changesBrian Paul
2009-04-03i965: rename scratch_buffer -> scratch_bo to be consistant with other buffersBrian Paul
2009-04-03i965: fix indentationBrian Paul
2009-04-03i965: whitespace changes, commentsBrian Paul
2009-03-28i965: srgb texture fixesRoland Scheidegger
i965 can either do SRGBA8_REV format or SARGB8 format, but not SRGBA8. Could add SRGBA8_REV support to mesa, but simply use SARGB8 for now. While here, also add true srgb luminance / luminance_alpha support - unfortunately the published docs fail to mention which asics support this, tested on g43 so assume this works on any g4x.
2009-03-28i965: add support for signed rgba texture formatRoland Scheidegger
2009-03-24i965: fix point rasterization when rendering to FBORobert Ellison
The FBO pixel coordinate system, with (0,0) as the upper-left pixel, is inverted in Y compared to the normal OpenGL pixel coordinate system, which has (0,0) as its lower-left pixel. Viewport and polygon stipple are sensitive to this inversion; so is point rasterization. The basic fix is simple: when rendering to an FBO, instead of the normal RASTRULE_UPPER_RIGHT that's appropriate for OpenGL windows, use the Y inversion RASTRULE_LOWER_RIGHT. Unfortunately, current Intel documentation has this value listed as "Reserved, but not seen as useful". It does work on at least some i965-class devices, though; and the worst that could happen if an older device didn't support it would be incorrect point rasterization to FBOs, which is what happens already, so this fix is at least no worse than what happens presently, and is better for some (and possibly all) i965-class devices.
2009-03-23i965: Fix glFrontFacing in twoside GLSL demo.Eric Anholt
This also cuts instructions by just using the existing bit in the payload rather than computing it from the determinant in the SF unit and passing it as a varying down to the WM. Something still goes wrong with getting the backface color right, but a simpler shader appears to get the right result.
2009-03-23i965: Fix fog coordinate g,b,a values when glFrontFacing isn't used.Eric Anholt
Previously, we would sample (f,glFrontFacing,undef,undef) instead of the (f,0,0,1) that fragment.fogcoord is supposed to return. Due to glFrontFacing's presence in FOGC.y, we'll still give bad results there when glFrontFacing is used. Bug #19122, piglit testcase fp-fog.
2009-03-23i965: Clean up a bit of mess with unneeded variables in emit_interp.Eric Anholt
2009-03-23i965: Fix occlusion query when no other WM state updates occur.Eric Anholt
Turns out that XXX comment was important. We weren't flagging the WM to re-update with the statistics enable, so we got zeroes out of our query. Bug #20740, fixes piglit occlusion_query test. Signed-off-by: Eric Anholt <eric@anholt.net>
2009-03-20Fix DRI2 accelerated EXT_texture_from_pixmap with GL_RGB format.Eric Anholt
This requires upgrading the interface so that the argument to glXBindTexImageEXT isn't just dropped on the floor. Note that this only fixes the accelerated path on Intel, as Mesa's texture format support is missing x8r8g8b8 support (right now, GL_RGB textures get uploaded as a8r8gb8, but in this case we're not doing the upload so we can't really work around it that way). Fixes bugs with compositors trying to use shaders that use alpha channels, on windows without a valid alpha channel. Bug #19910 and likely others as well. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2009-03-13i965: more register number assertionsBrian Paul