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path: root/src/mesa/drivers/dri/i965
AgeCommit message (Expand)Author
2010-10-08i965: Fix gen6 WM push constants updates.Eric Anholt
2010-10-08i965: Handle swizzles in the addition of YUV texture constants.Eric Anholt
2010-10-08i965: Drop the check for YUV constants in the param list.Eric Anholt
2010-10-08i965: Drop the check for duplicate _mesa_add_state_reference.Eric Anholt
2010-10-07i965: Normalize cubemap coordinates like is done in the Mesa IR path.Eric Anholt
2010-10-07i965: Disable emitting if () statements on gen6 until we really fix them.Eric Anholt
2010-10-06i965: Fix gen6 pointsize handling to match pre-gen6.Eric Anholt
2010-10-06i965: Don't assume that WPOS is always provided on gen6 in the new FS.Eric Anholt
2010-10-06i965: Add support for gl_FrontFacing on gen6.Eric Anholt
2010-10-06i965: Refactor gl_FrontFacing setup out of general variable setup.Eric Anholt
2010-10-06i965: Gen6's sampler messages are the same as Ironlake.Eric Anholt
2010-10-06i965: Don't do 1/w multiplication in new FS for gen6Eric Anholt
2010-10-06i965: Add some clarification of the WECtrl field.Eric Anholt
2010-10-06i965: Fix botch in the header_present case in the new FS.Eric Anholt
2010-10-06i965: Fix up IF/ELSE/ENDIF for gen6.Eric Anholt
2010-10-06i965: Gen6 no longer has the IFF instruction; always use IF.Eric Anholt
2010-10-06i965: Add back gen6 headerless FB writes to the new FS backend.Eric Anholt
2010-10-06i965: Also do constant propagation for the second operand of CMP.Eric Anholt
2010-10-06i965: Enable the constant propagation code.Eric Anholt
2010-10-04i965: Add support for gen6 FB writes to the new FS.Eric Anholt
2010-10-04i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.Eric Anholt
2010-10-04i965: Add initial folding of constants into operand immediate slots.Eric Anholt
2010-10-04i965: Add trivial dead code elimination in the new FS backend.Eric Anholt
2010-10-04i965: Be more conservative on live interval calculation.Eric Anholt
2010-10-03i965: Fix glean/texSwizzle regression in previous commit.Eric Anholt
2010-10-02i965: Set up swizzling of shadow compare results for GL_DEPTH_TEXTURE_MODE.Eric Anholt
2010-10-02i965: Add support for EXT_texture_swizzle to the new FS backend.Eric Anholt
2010-10-01i965: Fix incorrect batchbuffer size in gen6 clip state command.Kenneth Graunke
2010-10-01i965: Don't try to emit code if we failed register allocation.Eric Anholt
2010-10-01i965: Fix off-by-ones in handling the last members of register classes.Eric Anholt
2010-10-01i965: Add a sanity check for register allocation sizes.Eric Anholt
2010-10-01i965: When producing a single channel swizzle, don't make a temporary.Eric Anholt
2010-10-01i965: Restore the forcing of aligned pairs for delta_xy on chips with PLN.Eric Anholt
2010-10-01i965: Enable GL_ARB_texture_rgIan Romanick
2010-10-01i965: Fix up copy'n'pasteo from moving coordinate setup around for gen4.Eric Anholt
2010-10-01i965: Add real support for pre-gen5 texture sampling to the new FS.Eric Anholt
2010-10-01i965: Pre-gen6, map VS outputs (not FS inputs) to URB setup in the new FS.Eric Anholt
2010-10-01i965: Also increment attribute location when skipping unused slots.Eric Anholt
2010-10-01i965: Fix the gen6 jump size for BREAK/CONT in new FS.Eric Anholt
2010-10-01i965: Add gen6 attribute interpolation to new FS backend.Eric Anholt
2010-09-30i965: Split the gen4 and gen5 sampler handling apart.Eric Anholt
2010-09-30i965: Use the lowering pass for texture projection.Eric Anholt
2010-09-30i965: Fix new FS handling of builtin uniforms with packed scalars in structs.Eric Anholt
2010-09-30i965: Fix whole-structure/array assignment in new FS.Eric Anholt
2010-09-30dri/i965: remove duplicated includeNicolas Kaiser
2010-09-29i965: Remove my "safety counter" code from loops.Eric Anholt
2010-09-29i965: Add live interval analysis and hook it up to the register allocator.Eric Anholt
2010-09-29i965: First cut at register allocation using graph coloring.Eric Anholt
2010-09-29i965: Clean up the virtual GRF handling.Eric Anholt
2010-09-29i956: Make new FS discard do its work in a temp, not the null reg!Eric Anholt