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path: root/src/mesa/drivers/dri/i965
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2011-03-16i965c: add MESA_FORMAT_RGBA8888_REV to brw_format_for_mesa_formatChia-I Wu
The framebuffer uses PIXEL_FORMAT_BGRA_8888 -> MESA_FORMAT_ARGB8888 while applications use PIXEL_FORMAT_RGBA_8888 -> MESA_FORMAT_RGBA8888_REV PIXEL_FORMAT_RGB_565 -> MESA_FORMAT_RGB565
2011-03-16i965c: Fix a declaration in for loop.Chia-I Wu
2011-03-16i965c: Add support for GL_FIXED.Chia-I Wu
Quick and dirty..
2011-03-15i965: Fix alpha testing when there is no color buffer in the FBO.Eric Anholt
We were alpha testing against an unwritten value, resulting in garbage. (part of) Bug #35073.
2011-03-15i965: Do our lowering passes before the loop of optimization.Eric Anholt
The optimization loop won't reinsert noise instructions or quadop vectors, so we were traversing the tree for nothing. Lowering vector indexing was in the loop after do_common_optimization() to avoid the work if it ended up that the index was actually constant, but that has been called already in the core.
2011-03-14i965: Enable texture lookups whose return type is 'float'Kenneth Graunke
This enables the new shadow texture functions in GLSL 1.30. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Chad Versace <chad.versace@intel.com>
2011-03-14i965: Fix tex_swizzle when depth mode is GL_REDChad Versace
Change swizzle from (x000) to (x001). Signed-off-by: Chad Versace <chad.versace@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-03-14i965: Remove dead assignmentChad Versace
The assignment on line 368, `tex_swizzles[i] = SWIZZLE_NOOP`, is rendered dead by the reassignment on line 392. Signed-off-by: Chad Versace <chad.versace@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-03-12Revert "i965: Use the fixed function GLSL program instead of the ARB program."Eric Anholt
This reverts commit 81b34a4e3a7aec9cdf2781757408dc5e9eec79cb. There were regressions in the core change that this depends on.
2011-03-11i965: Use the fixed function GLSL program instead of the ARB program.Eric Anholt
This gets one more piece of the pipeline onto the new codegen backend. Once ARB_fragment_program can generate GLSL programs, we can nuke the old backend.
2011-03-11i965: Use ffs() on a 32-bit int value instad of ffsll().Eric Anholt
2011-03-09i965: Pack the tracked state atoms into separate arrays for prepare/emit.Chris Wilson
Improves performance of a hacked-up scissor-many (to reuse a small set of scissors instead of blowing out the cache, and then to run 100x more iterations so it actually took some time) by 3.6% +/- 1.2% (n=10)
2011-03-04i965: Apply a workaround for the Ironlake "vertex flashing".Eric Anholt
This is an awful hack and will hurt performance on Ironlake, but we're at a loss as to what's going wrong otherwise. This is the only common variable we've found that avoids the problem on 4 applications (CelShading, gnome-shell, Pill Popper, and my GLSL demo), while other variables we've tried appear to only be confounding. Neither the specifications nor the hardware team have been able to provide any enlightenment, despite much searching. https://bugs.freedesktop.org/show_bug.cgi?id=29172 Tested by: Chris Lord <chris@linux.intel.com> (Pill Popper) Tested by: Ryan Lortie <desrt@desrt.ca> (gnome-shell)
2011-03-04i965: Fix extending VB packetsChris Wilson
Computation of the delta of this array from the last had a silly little bug and ignored any initial delta==0 causing grief in Nexuiz and friends. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-04i965: Handle URB_FENCE erratum for BroadwaterChris Wilson
There is a silicon bug which causes unpredictable behaviour if the URB_FENCE command should cross a cache-line boundary. Pad before the command to avoid such occurrences. As this command only applies to gen4/5, do the fixup unconditionally as the specs do not actually state for which chip it was fixed (and the cost is negligible)... Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-04i965: Align index to type size and flush if the type changesChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-04i965: Prevent using a zero sized (or of unknown type) vertex arrayChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-03i965: SNB GT1 has only 32k urb and max 128 urb entries.Zou Nan hai
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
2011-03-02i965: Maxinum the usage of urb space on SNB.Zou Nan hai
SNB has 64k urb space, we only use piece of them. The more urb space we alloc, the more concurrent vs threads we can run. push the urb space usage to the limit. Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
2011-03-01i965: Use negative relocation deltas to minimse vertex uploadsChris Wilson
With relaxed relocation checking in the kernel, we can specify a negative delta (i.e. pointing outside of the target bo) in order to fake a range in a large buffer. We only then need to upload the elements used and adjust the buffer offset such that they correspond with the indices used in the DrawArrays. (Depends on libdrm 0209428b3918c4336018da9293cdcbf7f8fedfb6) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-01i965: Undo 'continuation of vb packets'Chris Wilson
This breaks nexuiz for unknown reason; disable until a true fix can be found.
2011-03-01i965: Fix uploading of shortened vertex packetsChris Wilson
... handle all cases and not just the interleaved upload. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-01i965: Upload all vertices usedChris Wilson
... and take advantage of start_vertex_bias to trim to [min_index, max_index] where possible (i.e. when we need to upload all arrays). Fixes half_float_vertex(misc.fillmode.wireframe) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34595 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-01Revert "i965/fs: Correctly set up gl_FragCoord.w on Sandybridge."Kenneth Graunke
This reverts commit 4a3b28113c3d23ba21bb8b8f5ebab7c567083a6d, as it caused a regression on Ironlake (bug #34646).
2011-03-01i965: bump VS thread number to 60 on SNBZou Nan hai
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
2011-02-25i965/fs: Initial plumbing to support TXD.Kenneth Graunke
This adds the opcode and the code to convert ir_txd to OPCODE_TXD; it doesn't actually add support yet.
2011-02-25i965/fs: Complete TXL support on gen5+.Kenneth Graunke
Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was never handled.
2011-02-25i965/fs: Complete TXL support on gen4.Kenneth Graunke
Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was never handled.
2011-02-25i965/fs: Use a properly named constant in TXB handling.Kenneth Graunke
The old value, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE makes it sound like we're doing a non-bias texture lookup. It has the same value as the new constant BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE, so there should be no functional changes.
2011-02-25i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.Kenneth Graunke
From volume 4, page 161 of the public i965 documentation.
2011-02-24i965: Increase Sandybridge point size clamp in the clip state.Kenneth Graunke
255.875 matches the hardware documentation. Presumably this was a typo. NOTE: This is a candidate for the 7.10 branch, along with commit 2bfc23fb86964e4153f57f2a56248760f6066033. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-24i965: Remember to pack the constant blend color as floats into the batchChris Wilson
Fixes regression from aac120977d1ead319141d48d65c9bba626ec03b8. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24intel: Reset the buffer offset after releasing reference to packed uploadChris Wilson
Fixes oglc/vbo(basic.bufferdata) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-24i965: Unmap the correct pointer after discontiguous uploadChris Wilson
Fixes piglit/fbo-depth-sample-compare: ==14722== Invalid free() / delete / delete[] ==14722== at 0x4C240FD: free (vg_replace_malloc.c:366) ==14722== by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695) ==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457) ==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394) ==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365) ==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389) ==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543) ==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973) ==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351) ==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd ==14722== at 0x4C244E8: malloc (vg_replace_malloc.c:236) ==14722== by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256) ==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457) ==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394) ==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365) ==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389) ==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543) ==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973) ==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351) ==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22i965: Increase Sandybridge point size clamp.Kenneth Graunke
255.875 matches the hardware documentation. Presumably this was a typo. Found by inspection. Not known to fix any issues. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22i965/fs: Correctly set up gl_FragCoord.w on Sandybridge.Kenneth Graunke
pixel_w is the final result; wpos_w is used on gen4 to compute it. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22i965/fs: Refactor control flow stack handling.Kenneth Graunke
We can't safely use fixed size arrays since Gen6+ supports unlimited nesting of control flow. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22i965/fs: Avoid register coalescing away gen6 MATH workarounds.Kenneth Graunke
The code that generates MATH instructions attempts to work around the hardware ignoring source modifiers (abs and negate) by emitting moves into temporaries. Unfortunately, this pass coalesced those registers, restoring the original problem. Avoid doing that. Fixes several OpenGL ES2 conformance failures on Sandybridge. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22i965/fs: Apply source modifier workarounds to POW as well.Kenneth Graunke
Single-operand math already had these workarounds, but POW (the only two operand function) did not. It needs them too - otherwise we can hit assertion failures in brw_eu_emit.c when code is actually generated. NOTE: This is a candidate for the 7.10 branch. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22i965: Fix shaders that write to gl_PointSize on Sandybridge.Kenneth Graunke
gl_PointSize (VERT_RESULT_PSIZ) doesn't take up a message register, as it's part of the header. Without this fix, writing to gl_PointSize would cause the SF to read and use the wrong attributes, leading to all kinds of random looking failure. Reviewed-by: Eric Anholt <eric@anholt.net>
2011-02-22i965: Trim the interleaved upload to the minimum number of verticesChris Wilson
... should have no impact on a properly formatted draw operation. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22i965: Reinstate max-index paranoiaChris Wilson
Don't trust the applications not to reference beyond the end of the vertex buffers. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-22i965: Zero the offset into the vbo when uploading non-interleavedChris Wilson
Fixes regression from 559435d9152acc7162e4e60aae6591c7c6c8274b. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-21i965: Fix VB packet reuse when offset for the new buffer isn't stride aligned.Eric Anholt
Fixes regression in scissor-stencil-clear and 5 other tests.
2011-02-21i965: Remove spurious duplicate ADVANCE_BATCHChris Wilson
... a leftover from a bad merge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-21i965: Use compiler builtins when availableChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-21i965: Micro-optimise check_stateChris Wilson
Replace the intermediate tests due to the logical or with the bitwise or. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-21i965: Remove unused 'next_free_page' memberChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-21intel: extend current vertex buffersChris Wilson
If the next vertex arrays are a (discontiguous) continuation of the current arrays, such that the new vertices are simply offset from the start of the current vertex buffer definitions we can reuse those defintions and avoid the overhead of relocations and invalidations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-21intel: Use specified alignment for writes into the upload bufferChris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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