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path: root/src/mesa/drivers/dri/intel/intel_batchbuffer.c
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2011-02-21intel: use throttle ioctl for throttlingChris Wilson
Rather than waiting on the first batch after the last swapbuffers to be retired, call into the kernel to wait upon the retirement of any request less than 20ms old. This has the twofold advantage of (a) not blocking any other clients from utilizing the device whilst we wait and (b) we attain higher throughput without overloading the system. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-21i965: Move repeat-instruction-suppression to batchbuffer coreChris Wilson
Move the tracking of the last emitted instructions into the core batchbuffer routines and take advantage of the shadow batch copy to avoid extra memory allocations and copies. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-21intel: use pwrite for batchChris Wilson
It's faster. Not only is the memcpy more efficiently performed in the kernel (making up for the system call overhead), but by not using mmap we remove the greater overhead of tracking the vma of every batch. And it means we can read back from the batch buffer without incurring the cost of a uncached read through the GTT. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-21intel: Buffered uploadChris Wilson
Rather than performing lots of little writes to update the common bo upon each update, write those into a static buffer and flush that when full (or at the end of the batch). Doing so gives a dramatic performance improvement over and above using mmaped access. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-21intel: Pack dynamic draws togetherChris Wilson
Dynamic arrays have the tendency to be small and so allocating a bo for each one is overkill and we can exploit many efficiency gains by packing them together. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-23i965: Use MI_FLUSH_DW for blt ring flush on sandybridgeZhenyu Wang
Old MI_FLUSH command is deprecated on sandybridge blt.
2010-12-13i965: Add support for using the BLT ring on gen6.Eric Anholt
2010-12-04intel: Add an env var override to execute for a different GPU revision.Eric Anholt
Sometimes I'm on the train and want to just read what's generated under INTEL_DEBUG=vs,wm for some code on another generation. Or, for the next gen enablement we'll want to dump aub files before we have the actual hardware. This will let us do that.
2010-11-03intel: Annotate debug printout checks with unlikely().Eric Anholt
This provides the optimizer with hints about code hotness, which we're quite certain about for debug printouts (or, rather, while we developers often hit the checks for debug printouts, we don't care about performance while doing so).
2010-11-02intel: For batch, use GTT mapping instead of writing to a malloc and copying.Eric Anholt
No measurable performance difference on cairo-perf-trace, but simplifies the code and should have cache benefit in general.
2010-09-28i965: sandybridge pipe control workaround before write cache flushZhenyu Wang
Must issue a pipe control with any non-zero post sync op before write cache flush = 1 pipe control.
2010-07-08intel: Update intel_decode.c from intel-gpu-tools.Eric Anholt
This came from commit cf255e382d147fe3ca450f0dcec3525190e7dcbc
2010-06-11i965: Add support for streaming indirect state rather than caching objects.Eric Anholt
2010-06-08intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc.Eric Anholt
The new API makes so much more sense, I'd like to forget how the old one worked.
2010-06-08intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.Eric Anholt
The slightly less mechanical change of converting the emit_reloc calls will follow.
2010-06-08intel: Clean up stale comments in intel_batchbuffer.c.Eric Anholt
2010-06-08intel: Remove the non-gem paths for batchbuffer upload.Eric Anholt
2010-05-31intel: Initialize batch->reserved_space on allocationChris Wilson
Fixes the assert (and buffer overrun): glknots: intel_batchbuffer.c:164: _intel_batchbuffer_flush: Assertion 'used >= batch->buf->size' failed. Reported in bug: Bug 28274 - xscreensaver's glknots hangs GPU (945GME/Pineview) https://bugs.freedesktop.org/show_bug.cgi?id=28274 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-05-28i965: fix PIPE_CONTROL command for gen6.Zou Nan hai
Signed-off-by: Zou Nan hai <nanhai.zou@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net>
2010-05-26i965: Don't PIPE_CONTROL instruction cache flush.Eric Anholt
This is a workaround for Ironlake errata. The emit_mi_flush is used for a few purposes: 1) Flushing write caches for RTT (including blit to texture) 2) Pipe fencing for sync objects 3) Spamming cache flushes to track down cache flush bugs Spamming cache flushes seems less important than following the docs, and we should probably do that with a different mechanism than the one for render cache flushes.
2010-05-20intel: Throttle after doing copyregion/swapbuffers round tripKristian Høgsberg
Before we would throttle in the flush callback prior to round-tripping to the server to do copyregion or swapbuffer. Now, instead just note that we need to throttle and do it in intel_prepare_render(), which will be called after receiving the response from the server but before we start rendering the next frame. Even if the server also throttles us in swapbuffer, this just makes the throttling a no-op when we hit intel_prepare_render(). With that we can drop the using_dri2_swapbuffers hack and just always throttle.
2010-05-18i965: Revert accidental debug change in 562e2d114ec0cba8Eric Anholt
2010-05-14i965: Support INTEL_DEBUG=clip to dump the clip program.Eric Anholt
2010-03-05intel: Move the assertions about reloc delta from the macros to the function.Eric Anholt
Cuts another 1800 bytes from the driver.
2010-03-03i915: Tell the kernel when we actually need fence registers on our BOs.Eric Anholt
This improves tiled texture performance of OA on my 945 from 25.3fps to 29.0fps, whereas untiled is 28.2fps, by avoiding stalls for fence register changes.
2010-02-25intel: Fix up INTEL_NO_HW support.Eric Anholt
This was accidentally (it seems) deleted in 5203b7227ccb6b618fa42f08434d4a3cf123dca2
2010-02-22intel: assert that we do not overflow the batch buffer.Chris Wilson
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-02-20intel: Silence compiler format warnings.Vinson Lee
2010-02-19Replace the _mesa_*printf() wrappers with the plain libc versionsKristian Høgsberg
2010-01-26intel: Clean up stale comments about cliprects.Eric Anholt
2010-01-25i965: Remove unnecessary malloc/free in VS binding table setup.Eric Anholt
2010-01-04intel: Drop batchbuffer cliprect_mode trackingKristian Høgsberg
2010-01-04intel: Drop LOCK/UNLOCK_HARDWARE()Kristian Høgsberg
2009-11-19intel: Remove non-GEM support.Eric Anholt
This really isn't supported at this point. GEM's been in the kernel for a year, and the fake bufmgr never really worked.
2009-11-19intel: Consistently use no_batch_wrap in intel_context struct.Eric Anholt
2009-11-06intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.Eric Anholt
This should do all the things that MI_FLUSH did, but it can be pipelined so that further rendering isn't blocked on the flush completion unless necessary.
2009-10-29intel: Clean up merge leftover from the DRI2 swap throttling.Eric Anholt
2009-08-05Merge branch 'mesa_7_5_branch'Brian Paul
Conflicts: src/mesa/main/state.c
2009-08-04intel: Wait on the last swapbuffers to complete before queuing a new one.Brian Paul
This fixes jerkiness in doom3 and other apps since the kernel change to throttle less absurdly, which led to a thundering herd of frames. Because this is a rather minimal fix, there is at least one downside: If the whole scene completes in one batchbuffer, we'll end up stalling the GPU. Thanks to Michel Dänzer for suggesting using glFlush to signal frame end instead of going to all the effort of adding a new DRI2 extension. (cherry picked from master, commit 0828579a658af01a64b5e699175dc9bbbedcd685)
2009-08-03intel: Wait on the last swapbuffers to complete before queuing a new one.Eric Anholt
This fixes jerkiness in doom3 and other apps since the kernel change to throttle less absurdly, which led to a thundering herd of frames. Because this is a rather minimal fix, there is at least one downside: If the whole scene completes in one batchbuffer, we'll end up stalling the GPU. Thanks to Michel Dänzer for suggesting using glFlush to signal frame end instead of going to all the effort of adding a new DRI2 extension.
2009-06-29intel: Make LOCK_HARDWARE recursive to avoid hand-rolling recursiveness.Eric Anholt
2009-03-05intel: Add always_flush_cache driconf option for debugging cache flush failure.Eric Anholt
I keep wanting to hack this knob in as a one-time thing, so it seemed useful to have all the time.
2008-11-11intel: reset cliprect_mode to IGNORE_CLIPRECTS.Xiang, Haihao
This ensures all batchbuffers have a same cliprect mode after calling _intel_batchbuffer_flush even if there aren't invalid commands in the current batch buffer. (fix bug#18362).
2008-10-28intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt
This avoids issues with dereferencing stale cliprects around intel_draw_buffer time. Additionally, take advantage of cliprects staying constant for FBOs and DRI2, and emit cliprects in the batchbuffer instead of having to flush batch each time they change.
2008-09-10intel: track move of bo_exec from drivers to bufmgr.Eric Anholt
2008-09-10intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.Eric Anholt
2008-09-10intel: Move the bufmgr back to the screen.Eric Anholt
Mesa requires that we be able to share objects between contexts, which means that the objects need to be created by the same bufmgr, and the bufmgr internally requires pthread protection for thread safety. Rely on the bufmgr having appropriate locking.
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-08intel-gem: Update to new check_aperture API for classic mode.Eric Anholt
To do this, I had to clean up some of 965 state upload stuff. We may end up over-emitting state in the aperture overflow case, but that should be rare, and I'd rather have the simplification of state management.