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Conflicts:
src/mesa/drivers/dri/radeon/radeon_fbo.c
src/mesa/drivers/dri/s3v/s3v_tex.c
src/mesa/drivers/dri/s3v/s3v_xmesa.c
src/mesa/drivers/dri/trident/trident_context.c
src/mesa/main/debug.c
src/mesa/main/mipmap.c
src/mesa/main/texformat.c
src/mesa/main/texgetimage.c
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Per the GLX spec, when changing rendering contexts, the old context
should first be flushed.
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_ActualFormat is replaced by Format (MESA_FORMAT_x).
ColorEncoding, ComponentType, RedBits, GreenBits, BlueBits, etc. are
all replaced by MESA_FORMAT_x queries.
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Conflicts:
src/gallium/auxiliary/util/u_cpu_detect.c
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Before, if we called glXMakeCurrent() to change a context's window binding
while an FBO was bound, we weren't updating the intel->driDrawable and
intel->driReadDrawable fields. This could cause us to dereference a null
pointer elsewhere.
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Since commit 2921a2555d0a76fa649b23c31e3264bbc78b2ff5 ('intel: Deassociated
drawables from private context struct in intelUnbindContext'),
intel->driDrawable may be NULL in intel_flush().
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This reverts commit 651cffd626a82d9bf539437ca4bdf8ea4b396fab.
The commit inadvertantly introduced a new gallium dependency on the meta code.
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Conflicts:
src/mesa/main/dlist.c
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The generic DRI infrastructure makes sure that __DRIcontextRec::driDrawablePriv
and __DRIcontextRec::driReadablePriv are set to NULL after unbinding a
context. However, the intel_context structure keeps cached copies of
these pointers. If these cached pointers are not NULLed and the
drawable is actually destroyed after unbinding the context (typically
by way of glXDestroyWindow), freed memory will be dereferenced in
intelDestroyContext.
This should fix bug #23418.
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These default swrast functions are already installed by
_mesa_init_driver_functions().
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Conflicts:
src/mesa/drivers/dri/intel/intel_context.c
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Hopefully this will be one of the last cherry-picks.
(cherry picked from commit ca246dd186f9590f6d67038832faceb522138c20)
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Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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This reverts commit e0ec405a9fa6fbc1cf2ac531ed5efd1a64e01f18.
This is already available in INTEL_DEBUG=bufmgr in the environment.
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(cherry picked from commit df70d3049a396af3601d2a1747770635a74120bb)
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We currently weasel out of supporting the timeout parameter, but otherwise
this extension looks ready, and should make the common case happy.
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The previous version of framebuffer blit was a quick hack. The new meta
version works pretty well.
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The comment disagreed with the code, and nicely drew my eyes to what was
going wrong.
Bug #21774 (blender)
Bug #21788 (readpix)
(cherry picked from master, commit fd65418f600874b05f902b622078b40bc1abb24a)
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This fixes jerkiness in doom3 and other apps since the kernel change to
throttle less absurdly, which led to a thundering herd of frames.
Because this is a rather minimal fix, there is at least one downside: If
the whole scene completes in one batchbuffer, we'll end up stalling the GPU.
Thanks to Michel Dänzer for suggesting using glFlush to signal frame end
instead of going to all the effort of adding a new DRI2 extension.
(cherry picked from master, commit 0828579a658af01a64b5e699175dc9bbbedcd685)
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The comment disagreed with the code, and nicely drew my eyes to what was
going wrong.
Bug #21774 (blender)
Bug #21788 (readpix)
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This fixes jerkiness in doom3 and other apps since the kernel change to
throttle less absurdly, which led to a thundering herd of frames.
Because this is a rather minimal fix, there is at least one downside: If
the whole scene completes in one batchbuffer, we'll end up stalling the GPU.
Thanks to Michel Dänzer for suggesting using glFlush to signal frame end
instead of going to all the effort of adding a new DRI2 extension.
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(cherry picked from commit ddef7dc87b2001fbe117ee5f24a0c645ee95a03c)
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Move all the metaops to a dri_metaops file and port radeon/intel
to use the new common meta ops code.
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1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
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This fixes a segfault seen with piglit's fdo20701 test.
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This reverts commit de447afff26706e3bf8bdcd5cfb8b1daf49b4b21 but
puts the lock under DRI1-only.
From keithw:
> It's there because the DRI1 code doesn't actually achieve the mutexing
> which it looks as if it should. For multi-threaded applications it was
> always possible to get two threads inside locked regions -- I have no
> idea how, but it certainly was and presumably still is possible.
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This would cause LOCK_HARDWARE to mutex all contexts in this process on
both DRI1 and DRI2. On DRI1, LOCK_HARDWARE already does it for all
processes on the system. On DRI2, LOCK_HARDWARE doesn't, but there shouldn't
be any state outside the context that needs any additional protection.
Notably, the bufmgr is protected by its own mutex and not
LOCK_HARDWARE.
This code was originally introduced with the i915tex code dump, so it's not
clear what it was there for.
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To maintain correctness, the server will copy the real front-buffer to
a newly allocated fake front-buffer in DRI2GetBuffersWithFormat.
However, if the DRI2GetBuffersWithFormat is triggered by glViewport,
this will copy stale data into the new buffer. Fix this by flushing
the current fake front-buffer to the real front-buffer in
intel_viewport.
Fixes bug #22288.
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(cherry picked from commit d4a42b0ce6455d03be70aa56aacd779be193aca4)
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Conflicts:
Makefile
src/gallium/drivers/softpipe/sp_screen.c
src/mesa/main/version.h
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Initialize all driver function hooks before calling _mesa_initialize_context(),
and handle all buffer objects in intel_buffer_object().
Fixes assertion failure when running glxinfo.
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The early Z stuff is supposed to be unsafe without some more work in the
enable/disable path (in particular, how do we want to get it disabled on
the way out to the X Server?), but at the moment is 6% in OA.
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This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
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