| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2008-09-10 | intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change. | Eric Anholt | |
| 2008-09-03 | intel: Fix prototype warning. | Eric Anholt | |
| 2008-08-29 | DRI2: Drop sarea, implement swap buffers in the X server. | Kristian Høgsberg | |
| 2008-08-24 | Revert "Revert "Merge branch 'drm-gem'"" | Dave Airlie | |
| This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a. | |||
| 2008-08-24 | Revert "Merge branch 'drm-gem'" | Dave Airlie | |
| This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c | |||
| 2008-08-08 | intel-gem: Update to new check_aperture API for classic mode. | Eric Anholt | |
| To do this, I had to clean up some of 965 state upload stuff. We may end up over-emitting state in the aperture overflow case, but that should be rare, and I'd rather have the simplification of state management. | |||
| 2008-07-11 | drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes. | Eric Anholt | |
| 2008-07-01 | intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode. | Eric Anholt | |
| It turns out that it's not just deviceID dependent, and there's some additional undefined factor that determines the bit 6 swizzling. It's now controllable with swizzle_mode=[012] until we get a response on how to automatically detect. | |||
| 2008-06-24 | Merge commit 'origin/master' into drm-gem | Eric Anholt | |
| 2008-06-23 | i915: Accumulate the VB into a local buffer and subdata it in. | Eric Anholt | |
| This lets GEM use pwrite, for an additional 4% or so speedup. | |||
| 2008-06-23 | i915: Convert to using VBs instead of inline prims. | Eric Anholt | |
| 2008-06-21 | replace __inline and __inline__ with INLINE macro | Brian Paul | |
| 2008-06-03 | [intel] Convert drivers to using libdrm bufmgr code. | Eric Anholt | |
| 2008-05-02 | [intel] Fix build for GEM. TTM is now disabled, and fencing is gone. | Eric Anholt | |
| Fencing was used in two places: ensuring that we didn't get too many frames ahead of ourselves, and glFinish. glFinish will be satisfied by waiting on buffers like we would do for CPU access on them. The "don't get too far ahead" is now the responsibility of the execution manager (kernel). | |||
| 2008-03-13 | [i965] multiple rendering target support | Zou Nan hai | |
| 2008-03-05 | [intel] Add a driconf option to cache freed buffer objects for reuse. | Eric Anholt | |
| This is defaulted off as it has potentially large memory costs for a modest performance gain. Ideally we will improve DRM performance to the point where this optimization is not worth the memory cost in any case, or find some middle ground in caching only limited numbers of certain buffers. For now, this provides a modest 4% improvement in openarena on GM965 and 10% in openarena on GM945. | |||
| 2008-02-27 | intel: Always use intelInitExtensions() for initializing extensions. | Kristian Høgsberg | |
| 2008-02-22 | Merge {i915,i965}/intel_context.h as intel/intel_context.h | Kristian Høgsberg | |
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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