summaryrefslogtreecommitdiff
path: root/src/mesa/drivers/dri/intel/intel_fbo.h
AgeCommit message (Collapse)Author
2009-04-16intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.Eric Anholt
Also enable them all regardless of screen bpp, as 32 bpp what I've been testing against, and haven't been able to detect any screen bpp-specific troubles with them.
2009-01-30intel: remove unused RenderToTexture fieldBrian Paul
2009-01-29intel: remove unused intel_rendering_to_texture()Brian Paul
2009-01-27intel: clean up more pf mess.Eric Anholt
2009-01-22intel: remove/disable the "paired depth/stencil" codeBrian Paul
We only allow combined depth+stencil renderbuffers so the complicated code for splitting and combining separate depth and stencil buffers is no longer needed.
2009-01-22intel: inline some renderbuffer functionsBrian Paul
2009-01-20Remove intel pageflipping support in its entirety.Owain G. Ainsworth
It's been broken and deprecated for a while, so it's time to die. This has the wonderful benefit of cleaning up the code a fair amount; making it marginally less twisty. I'm unsure if the for loops in IntelWindowMoved are still needed.
2009-01-16intel: added intel_rendering_to_texture() helper function.Brian Paul
When we're rendering to textures we have to invert the viewport transformation. This helper cleans up that test and can be used elsewhere...
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-07-23intel: Add a little span cache to spead up readpixels by cutting syscalls.Eric Anholt
2008-07-23intel-gem: Use pread/pwrite for span access.Eric Anholt
This will avoid clflushing entire buffers for small acesses, such as those commonly used by regression tests.
2008-07-11drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt
2008-07-02intel-gem: Fix Y-tiling span setup.Eric Anholt
The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8.
2008-05-06[intel-GEM] Add tiling support to swrast.Keith Packard
Accessing tiled surfaces without using the fence registers requires that software deal with the address swizzling itself.
2008-02-15[intel] Allow attIndex to be negative to avoid defeating the >= 0 check.Eric Anholt
Otherwise, we would go wildly out of bounds if passed -1 (no renderbuffer), such as while doing LOCK_HARDWARE with glDrawBuffer(GL_NONE).
2008-01-09[intel] Simplify intelCreateBuffer() a bit.Kristian Høgsberg
Drop a bunch of unused arguments from intel_create_renderbuffer() and introduce intel_renderbuffer_set_region() to set the region for a renderbuffer.
2007-11-16[intel] Move additional code to be shared from intel_context.h to intel/.Eric Anholt
2007-11-09[intel] Move over files that will be shared with 965-fbo work.Eric Anholt