| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-12-23 | i965: Use MI_FLUSH_DW for blt ring flush on sandybridge | Zhenyu Wang | |
| Old MI_FLUSH command is deprecated on sandybridge blt. | |||
| 2010-09-28 | i965: sandybridge pipe control workaround before write cache flush | Zhenyu Wang | |
| Must issue a pipe control with any non-zero post sync op before write cache flush = 1 pipe control. | |||
| 2010-06-10 | i965: Add support for GL_ALPHA framebuffer objects. | Eric Anholt | |
| 2010-03-18 | intel: Correct value of S0_VB_OFFSET_MASK to match hardware docs. | Ian Romanick | |
| 2009-06-04 | i915: Don't rely on fence regs when we don't have to. | Eric Anholt | |
| We're on the way to telling the kernel about when we need fence regs on our objects or not, and this will cut the number of places needing them. | |||
| 2008-12-02 | intel: restore old vertex submit paths for i8xx hardware. | Dave Airlie | |
| Intel docs state that only 830/845 have VBOs, 855/865 don't. So lets just not use them on i8xx at all. This restores the old pre-vbo code and uses it on all 8xx hw. | |||
| 2008-11-20 | intel: fix i830 comment + backwards VB offsets. | airlied | |
| According to Keith the docs have these offsets the other way around | |||
| 2008-11-20 | intel: fix i8xx vbo enable bit | airlied | |
| 2008-10-28 | intel: Don't keep intel->pClipRects, and instead just calculate it when needed. | Eric Anholt | |
| This avoids issues with dereferencing stale cliprects around intel_draw_buffer time. Additionally, take advantage of cliprects staying constant for FBOs and DRI2, and emit cliprects in the batchbuffer instead of having to flush batch each time they change. | |||
| 2008-10-07 | i965: Add ARB_occlusion_query support. | Eric Anholt | |
| 2008-08-24 | Revert "Revert "Merge branch 'drm-gem'"" | Dave Airlie | |
| This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a. | |||
| 2008-08-24 | Revert "Merge branch 'drm-gem'" | Dave Airlie | |
| This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c | |||
| 2008-06-23 | i915: Convert to using VBs instead of inline prims. | Eric Anholt | |
| 2008-05-23 | Emit a flush after the swapbuffers blit, so contents end up on the screen. | Eric Anholt | |
| Otherwise, since the MI_FLUSH at the end of every batch had been removed, non-automatic-flushing chips (965) wouldn't get flushed and apps with static rendering would get partial screen contents until the server's blockhandler flush kicked in. | |||
| 2007-12-20 | [965] Enable EXT_framebuffer_object. | Eric Anholt | |
| To do so, merge the remainnig necessary code from the buffers, blit, span, and screen code to shared, and replace it with those. | |||
| 2007-11-12 | i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730 | Xiang, Haihao | |
| 2007-10-04 | Replace duplicated intel_reg.h with a shared header. | Eric Anholt | |
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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