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path: root/src/mesa/drivers/dri/intel/intel_regions.c
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2009-11-19intel: Remove non-GEM support.Eric Anholt
This really isn't supported at this point. GEM's been in the kernel for a year, and the fake bufmgr never really worked.
2009-11-06Make a convenient int for what chipset generation we're on.Eric Anholt
gen2/3/4 are easier to say than "8xx, 915-945/g33/pineview, 965/g45/misc", and compares on generation are often easier than stringing together a bunch of chipset checks.
2009-09-09Merge branch 'mesa_7_5_branch' into mesa_7_6_branchBrian Paul
Conflicts: Makefile configs/default progs/glsl/Makefile src/gallium/auxiliary/util/u_simple_shaders.c src/gallium/state_trackers/glx/xlib/xm_api.c src/mesa/drivers/dri/i965/brw_draw_upload.c src/mesa/drivers/dri/i965/brw_vs_emit.c src/mesa/drivers/dri/intel/intel_context.h src/mesa/drivers/dri/intel/intel_pixel.c src/mesa/drivers/dri/intel/intel_pixel_read.c src/mesa/main/texenvprogram.c src/mesa/main/version.h
2009-09-04intel: Align untiled region height to 2 according to 965 docs.Eric Anholt
This may or may not be required pre-965, but it doesn't seem unlikely, and I'd rather be safe. (cherry picked from commit b053474378633249be0e9f24010650ffb816229a)
2009-08-19intel: Align untiled region height to 2 according to 965 docs.Eric Anholt
This may or may not be required pre-965, but it doesn't seem unlikely, and I'd rather be safe.
2009-08-07intel: Align region height as required for tiled regions.Eric Anholt
Otherwise, we would address beyond the end of our buffers. Fixes reliable GPU segfault with texture_tiling=true and oglconform shadow.c. Bug #22406.
2009-08-07intel: move blit call out of assert()Brian Paul
2009-07-02intel: Flush when mapping buffer objects so writes don't get reordered.Eric Anholt
While GEM covers this for execution it knows about, it doesn't know about the batchbuffer we're preparing. Fixes piglit vbo-map-remap.c testcase.
2009-06-29intel: Make LOCK_HARDWARE recursive to avoid hand-rolling recursiveness.Eric Anholt
2009-06-23intel: Avoid trying to do blits to Y tiled regions.Eric Anholt
This is somewhat nasty, but we need to do Y-tiled depth for FBO support. May help with corruption and hangs since enabling texture tiling, and since switching depth textures to Y tiled. Fixes piglit depthtex.c on 965.
2009-06-23intel: Fix some potential writes to zero-copy PBOs when used as regions.Eric Anholt
I was in the midst of fixing some blitting-with-Y-tiled issues when I noticed this. Hopefully PBO usage will be a little more robust, as a result.
2009-06-23intel: Remove long-unused intel_region_fill and intelEmitFillBlit.Eric Anholt
2009-06-19intel: Don't map regions with drm_intel_gem_bo_map_gtt() unless they're tiled.Eric Anholt
This fixes a regression in region read performance that came in with the texture tiling changes. Ideally we'd have an access flag coming in so we could also use bo_map_gtt for writing, like we do for buffer objects. Bug #22190
2009-06-19intel: Do not access pbo's buffer directly when attaching.Chia-I Wu
pbo might be system buffer based or attached to another region. Call intel_bufferobj_buffer to make sure pbo has a buffer of its own. Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-06-19intel: Data are copied in the wrong direction when breaking COW tie.Chia-I Wu
Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net>
2009-06-17i965: Fix tiling for FBO depth attachments by making DEPTH_COMPONENT Y tiled.Eric Anholt
This may hurt if miptree relayout occurs, since we can't blit Y tiled objects. But it corrects depth tests on FBOs using textures.
2009-06-09intel: Fix intel_region_unmap to do unmap, not map.Eric Anholt
Thanks to Shuang He for catching this.
2009-06-04intel: Add support for tiled textures.Eric Anholt
This is about a 30% performance win in OA with high settings on my GM45, and experiments with 915GM indicate that it'll be around a 20% win there. Currently, 915-class hardware is seriously hurt by the fact that we use fence regs to control the tiling even for 3D instructions that could live without them, so we spend a bunch of time waiting on previous rendering in order to pull fences off. Thus, the texture_tiling driconf option defaults off there for now.
2009-05-08i965: improve debug loggingRobert Ellison
Looking for memory leaks that were causing crashes in my environment in a situation where valgrind would not work, I ended up improving the i965 debug traces so I could better see where the memory was being allocated and where it was going, in the regions and miptrees code, and in the state caches. These traces were specific enough that external scripts could determine what elements were not being released, and where the memory leaks were. I also ended up creating my own backtrace code in intel_regions.c, to determine exactly where regions were being allocated and for what, since valgrind wasn't working. Because it was useful, I left it in, but disabled and compiled out. It can be activated by changing a flag at the top of the file.
2009-02-26i965: add missing init for region->widthBrian Paul
This doesn't seem to really effect anything but seeing width=0 in drawing regions was confusing.
2009-02-21intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions.Eric Anholt
This lets us avoid allocing new buffers for renderbuffers, finalized miptrees, and PBO-uploaded textures when there's an unreferenced but still active one cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded textures. The size of BOs allocated for a desktop running current GL cairogears on i915 is cut in half with this. Note that this means we require libdrm 2.4.5.
2009-01-30intel: more debug infoBrian Paul
2008-12-23Remove third buffer support from Mesa.Dave Airlie
This is part of the deprecated pageflipping infrastructure.
2008-10-27intel: Use dri_bo_get_tiling to get tiling mode of buffers we get from names.Eric Anholt
Previously, we were trying to pass a name to the GEM GET_TILING_IOCTL, which needs a handle, and failing. None of our buffers were tiled yet, but they will be at some point with DRI2 and UXA.
2008-09-26intel: Fix a number of memory leaks on context destroy.Eric Anholt
2008-09-12intel: Add a width field to regions, and use it for making miptrees in TFP.Eric Anholt
Otherwise, we would use the pitch as width of the texture, and compiz would render the pitch padding on the right hand side.
2008-09-10intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.Eric Anholt
2008-08-29DRI2: Drop sarea, implement swap buffers in the X server.Kristian Høgsberg
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-14intel: remove unneeded mem type and argsDave Airlie
2008-07-11drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt
2008-06-26intel: Fix locking when doing intel_region_cow().Eric Anholt
This was broken in the merge of 965 blit support. It tried to lock only when things were already locked.
2008-06-26intel: Replace sprinkled intel_batchbuffer_flush with MI_FLUSH or nothing.Eric Anholt
Most of these were to ensure that caches got synchronized between 2d (or meta) rendering and later use of the target as a source, such as for texture miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(), which just drops an MI_FLUSH. Most of the remainder were to ensure that REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped. Those are now replaced by automatically flushing those when dropping the lock.
2008-06-03[intel] Convert drivers to using libdrm bufmgr code.Eric Anholt
2008-05-02[intel] Fix build for GEM. TTM is now disabled, and fencing is gone.Eric Anholt
Fencing was used in two places: ensuring that we didn't get too many frames ahead of ourselves, and glFinish. glFinish will be satisfied by waiting on buffers like we would do for CPU access on them. The "don't get too far ahead" is now the responsibility of the execution manager (kernel).
2008-02-14Hook up i915 driver to new DRI2 infrastructure.Kristian Høgsberg
2008-02-05[965] Bug 14314: assertion failure with with !AIGLX and depth=24 visual.Eric Anholt
2008-02-04Replace usage of DRM_BO_FLAG_MEM_TT in intel_regions.c with local/cached.Eric Anholt
In addition to potentially binding when it was about to be mapped anyway, failure to use CACHED_MAPPED means eating a full wbinvd on validate. Thanks to airlied for catching this.
2008-02-01 [intel] use _mesa_copy_rect for upload compressed texture,Zou Nan hai
this fix bad texture issue in some games(UT and quake).
2008-01-22[intel] Clean up references to screen buffer metrics.Kristian Høgsberg
The screen wide info such as pitch and cpp are obsoleted by the FBO changes, so clean up the last few references to those, except for setting up the legacy screen regions.
2007-12-15[intel] Merge intel_buffer_objects to shared.Eric Anholt
965 gains fixed TTM typing of the buffer object buffers and unused PBO functions, and 915 gains buffer size == 0 fixes from 965.
2007-12-15[965] Use shared intel_regions.c.Eric Anholt
This adds (so far) unused PBO functions, and holding the lock while writing to regions (which may be shared static screen regions).
2007-12-14[intel] Remove useless intel_region_idle.Eric Anholt
The idling it was trying to ensure was covered by the intel_miptree_image_map()->intel_region_map() that immediately followed it.
2007-12-12[intel] Move bufmgr back to context instead of screen, fixing glthreads.Eric Anholt
Putting the bufmgr in the screen is not thread-safe since the emit_reloc changes. It also led to a significant performance hit from pthread usage for the attempted thread-safety (up to 12% of a cpu spent on refcounting protection in single-threaded 965). The motivation had been to allow multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
2007-11-16[intel] Add 965 support to shared intel_blit.cEric Anholt
This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine.
2007-11-16[i915] Pass static region names in so debugging says more than "static region".Eric Anholt
2007-11-09[intel] Move over files that will be shared with 965-fbo work.Eric Anholt