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path: root/src/mesa/drivers/dri/intel/intel_regions.h
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2009-10-23intel: Keep track of x,y offsets in miptrees and use them for blitting.Eric Anholt
By just using offsets, we confused the hardware's tiling calculations, resulting in failures in miptree validation and blit clears. Fixes piglit fbo-clearmipmap. Bug #23552. (automatic mipmap generation)
2009-06-23intel: Avoid trying to do blits to Y tiled regions.Eric Anholt
This is somewhat nasty, but we need to do Y-tiled depth for FBO support. May help with corruption and hangs since enabling texture tiling, and since switching depth textures to Y tiled. Fixes piglit depthtex.c on 965.
2009-06-23intel: Fix some potential writes to zero-copy PBOs when used as regions.Eric Anholt
I was in the midst of fixing some blitting-with-Y-tiled issues when I noticed this. Hopefully PBO usage will be a little more robust, as a result.
2009-06-23intel: Remove long-unused intel_region_fill and intelEmitFillBlit.Eric Anholt
2009-06-04intel: Add support for tiled textures.Eric Anholt
This is about a 30% performance win in OA with high settings on my GM45, and experiments with 915GM indicate that it'll be around a 20% win there. Currently, 915-class hardware is seriously hurt by the fact that we use fence regs to control the tiling even for 3D instructions that could live without them, so we spend a bunch of time waiting on previous rendering in order to pull fences off. Thus, the texture_tiling driconf option defaults off there for now.
2009-02-21intel: tell libdrm whether we want a cpu-ready or gpu-ready BO for regions.Eric Anholt
This lets us avoid allocing new buffers for renderbuffers, finalized miptrees, and PBO-uploaded textures when there's an unreferenced but still active one cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded textures. The size of BOs allocated for a desktop running current GL cairogears on i915 is cut in half with this. Note that this means we require libdrm 2.4.5.
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul
Makefile.template
2008-09-12intel: Add a width field to regions, and use it for making miptrees in TFP.Eric Anholt
Otherwise, we would use the pitch as width of the texture, and compiz would render the pitch padding on the right hand side.
2008-09-10intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.Eric Anholt
2008-08-29DRI2: Drop sarea, implement swap buffers in the X server.Kristian Høgsberg
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-07-11drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt
2008-02-14Hook up i915 driver to new DRI2 infrastructure.Kristian Høgsberg
2008-02-01 [intel] use _mesa_copy_rect for upload compressed texture,Zou Nan hai
this fix bad texture issue in some games(UT and quake).
2007-12-14[intel] Remove useless intel_region_idle.Eric Anholt
The idling it was trying to ensure was covered by the intel_miptree_image_map()->intel_region_map() that immediately followed it.
2007-12-12[intel] Move bufmgr back to context instead of screen, fixing glthreads.Eric Anholt
Putting the bufmgr in the screen is not thread-safe since the emit_reloc changes. It also led to a significant performance hit from pthread usage for the attempted thread-safety (up to 12% of a cpu spent on refcounting protection in single-threaded 965). The motivation had been to allow multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
2007-11-16[intel] Add 965 support to shared intel_blit.cEric Anholt
This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine.
2007-11-16[i915] Pass static region names in so debugging says more than "static region".Eric Anholt
2007-11-09[intel] Move over files that will be shared with 965-fbo work.Eric Anholt