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path: root/src/mesa/drivers/dri/intel/intel_span.c
AgeCommit message (Expand)Author
2008-08-05dri: Fix write/read depth buffer issue under 16bpp mode. See bug #16646Xiang, Haihao
2008-07-26intel: Don't return a renderbuffer with alpha when just GL_RGB is requested.Eric Anholt
2008-07-23intel: Add a little span cache to spead up readpixels by cutting syscalls.Eric Anholt
2008-07-23intel-gem: Use pread/pwrite for span access.Eric Anholt
2008-07-23intel: move renderbuffer mapping to separate functions.Eric Anholt
2008-07-15intel-gem: Disable spantmp sse/mmx functions when tile swizzling.Eric Anholt
2008-07-11drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt
2008-07-02intel: span rendering requires just a flush before starting, not finish.Eric Anholt
2008-07-02intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.Eric Anholt
2008-07-02intel-gem: Fix Y-tiling span setup.Eric Anholt
2008-07-01intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.Eric Anholt
2008-06-17[intel-gem] Bug #16326: Fix X tile unswizzling on 965.Eric Anholt
2008-05-06[intel-GEM] Add tiling support to swrast.Keith Packard
2008-01-10i965: fix segfault caused by commit e131c46b20241737ceba4856dbe01dcca6dd2c03.Xiang, Haihao
2008-01-06Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.Brian
2007-12-12[intel] Move bufmgr back to context instead of screen, fixing glthreads.Eric Anholt
2007-11-09[intel] Move over files that will be shared with 965-fbo work.Eric Anholt