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path: root/src/mesa/drivers/dri/intel/intel_span.c
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2009-10-28Merge branch 'texformat-rework'Brian Paul
Conflicts: src/mesa/drivers/dri/radeon/radeon_fbo.c src/mesa/drivers/dri/s3v/s3v_tex.c src/mesa/drivers/dri/s3v/s3v_xmesa.c src/mesa/drivers/dri/trident/trident_context.c src/mesa/main/debug.c src/mesa/main/mipmap.c src/mesa/main/texformat.c src/mesa/main/texgetimage.c
2009-10-28Merge branch 'mesa_7_6_branch'Brian Paul
Conflicts: src/mesa/shader/lex.yy.c src/mesa/shader/program_lexer.l
2009-10-27intel: added region draw_x/y offsets in x/y_tile_swizzle() funcsBrian Paul
This fixes the second part of bug 23552.
2009-10-21intel: use MESA_FORMAT_S8_Z24 format and avoid z24s8/s8z24 conversionsBrian Paul
2009-10-08mesa: remove a bunch of gl_renderbuffer fieldsBrian Paul
_ActualFormat is replaced by Format (MESA_FORMAT_x). ColorEncoding, ComponentType, RedBits, GreenBits, BlueBits, etc. are all replaced by MESA_FORMAT_x queries.
2009-10-05drivers: don't include texformat.hBrian Paul
And remove other unneeded #includes while we're at it.
2009-10-01i915: Enable ARB_vertex_shader for both i915 and i830.Eric Anholt
Since the TNL is all done in software anyway, it should be the same to the user who's probably using ARB_vertex_program otherwise, but gives them a nicer programming environment.
2009-09-30mesa: replace gl_texture_format with gl_formatBrian Paul
Now gl_texture_image::TexFormat is a simple MESA_FORMAT_x enum. ctx->Driver.ChooseTexture format also returns a MESA_FORMAT_x. gl_texture_format will go away next.
2009-09-14intel: minor code clean-upsBrian Paul
2009-09-14intel: fix renderbuffer map/unmap regressionBrian Paul
Commit 36dd53a3cded9d003ec418732b7fc93c1476aa9b caused a few regressions because the glReadBuffer() buffer wasn't getting mapped when GL_READ_BUFFER != GL_DRAW_BUFFER.
2009-09-10intel: Don't forget to map the depth read buffer in spans.Eric Anholt
This broke BlitFramebufferEXT(GL_DEPTH_BUFFER_BIT).
2009-08-07intel: fix typo: s/softare/software/Brian Paul
2009-04-16intel: Add support for argb1555, argb4444 FBOs and fix rgb565 fbo readpixels.Eric Anholt
Also enable them all regardless of screen bpp, as 32 bpp what I've been testing against, and haven't been able to detect any screen bpp-specific troubles with them.
2009-02-26intel: Add span code for z24 without stencil.Eric Anholt
It seems that in this case the Mesa code is handing us x8z24 values instead of z24s8 values, so we need to not do the rotation. Fixes half of OGLconform depthrange.c. Bug #19447.
2009-02-25intel: make template wrappers for the spans templates.Eric Anholt
This is insanity, but so is copying the same blocks containing the actual interesting code in the file three times each for the different tile formats.
2009-01-29intel: fix check for Y orientation in span functions.Brian Paul
2009-01-27intel: clean up more pf mess.Eric Anholt
2009-01-14intel: SW fallback maps texture images, not texture coordinatesIan Romanick
2008-10-28intel: Don't keep intel->pClipRects, and instead just calculate it when needed.Eric Anholt
This avoids issues with dereferencing stale cliprects around intel_draw_buffer time. Additionally, take advantage of cliprects staying constant for FBOs and DRI2, and emit cliprects in the batchbuffer instead of having to flush batch each time they change.
2008-09-18mesa: added "main/" prefix to includes, remove some -I paths from ↵Brian Paul
Makefile.template
2008-09-10intel: track move of bo_exec from drivers to bufmgr.Eric Anholt
2008-08-24Revert "Revert "Merge branch 'drm-gem'""Dave Airlie
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
2008-08-24Revert "Merge branch 'drm-gem'"Dave Airlie
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
2008-08-08Merge branch 'drm-gem'Eric Anholt
Conflicts: src/mesa/drivers/dri/intel/intel_span.c src/mesa/main/fbobject.c This converts the i915 driver to use the GEM interfaces for object management.
2008-08-05dri: Fix write/read depth buffer issue under 16bpp mode. See bug #16646Xiang, Haihao
2008-07-26intel: Don't return a renderbuffer with alpha when just GL_RGB is requested.Eric Anholt
Fixes oglconform rbGetterFuncs testcase. The span code for this mode hasn't actually been tested.
2008-07-23intel: Add a little span cache to spead up readpixels by cutting syscalls.Eric Anholt
2008-07-23intel-gem: Use pread/pwrite for span access.Eric Anholt
This will avoid clflushing entire buffers for small acesses, such as those commonly used by regression tests.
2008-07-23intel: move renderbuffer mapping to separate functions.Eric Anholt
This lets us avoid duplicated code for doing so, including the depthstencil paths that aren't covered by SpanRenderStart/Finish. Those paths were missing the span funcs setup, leading to a null dereference in the fbotexture demo.
2008-07-15intel-gem: Disable spantmp sse/mmx functions when tile swizzling.Eric Anholt
Those functions rely on being able to treat the GET_PTR returned value as an array indexed by x, but that's not the case for our tiling. Bug #16387
2008-07-11drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt
2008-07-02intel: span rendering requires just a flush before starting, not finish.Eric Anholt
The dri_bo_map()s that follow will take care of idling the hardware as needed.
2008-07-02intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.Eric Anholt
Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now displays correctly.
2008-07-02intel-gem: Fix Y-tiling span setup.Eric Anholt
The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8.
2008-07-01intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.Eric Anholt
It turns out that it's not just deviceID dependent, and there's some additional undefined factor that determines the bit 6 swizzling. It's now controllable with swizzle_mode=[012] until we get a response on how to automatically detect.
2008-06-17[intel-gem] Bug #16326: Fix X tile unswizzling on 965.Eric Anholt
Apparently a bit gets flipped in the addressing for some rows of each tile.
2008-05-06[intel-GEM] Add tiling support to swrast.Keith Packard
Accessing tiled surfaces without using the fence registers requires that software deal with the address swizzling itself.
2008-01-10i965: fix segfault caused by commit e131c46b20241737ceba4856dbe01dcca6dd2c03.Xiang, Haihao
2008-01-06Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.Brian
These fields are no longer indexed by shader output. Now, we just have a simple array of renderbuffer pointers. If the shader writes to gl_FragData[i], send those colors to the N _ColorDrawBuffers. Otherwise, replicate the single gl_FragColor (or the fixed-function color) to the N _ColorDrawBuffers. A few more changes and simplifications can follow from this...
2007-12-12[intel] Move bufmgr back to context instead of screen, fixing glthreads.Eric Anholt
Putting the bufmgr in the screen is not thread-safe since the emit_reloc changes. It also led to a significant performance hit from pthread usage for the attempted thread-safety (up to 12% of a cpu spent on refcounting protection in single-threaded 965). The motivation had been to allow multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
2007-11-09[intel] Move over files that will be shared with 965-fbo work.Eric Anholt