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path: root/src/mesa/drivers/dri/intel/intel_span.c
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2008-07-23intel-gem: Use pread/pwrite for span access.Eric Anholt
This will avoid clflushing entire buffers for small acesses, such as those commonly used by regression tests.
2008-07-23intel: move renderbuffer mapping to separate functions.Eric Anholt
This lets us avoid duplicated code for doing so, including the depthstencil paths that aren't covered by SpanRenderStart/Finish. Those paths were missing the span funcs setup, leading to a null dereference in the fbotexture demo.
2008-07-15intel-gem: Disable spantmp sse/mmx functions when tile swizzling.Eric Anholt
Those functions rely on being able to treat the GET_PTR returned value as an array indexed by x, but that's not the case for our tiling. Bug #16387
2008-07-11drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.Eric Anholt
2008-07-02intel: span rendering requires just a flush before starting, not finish.Eric Anholt
The dri_bo_map()s that follow will take care of idling the hardware as needed.
2008-07-02intel-gem: Fix y-tile swizzling for our G965 with swizzle_mode=1.Eric Anholt
Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now displays correctly.
2008-07-02intel-gem: Fix Y-tiling span setup.Eric Anholt
The boolean that the server gives us for whether the region is tiled was getting used as the enum for what tiling mode. Instead, guess the correct tiling in screen setup. Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is 32 scanlines, not 8.
2008-07-01intel-gem: Move bit 6 x tiling swizzle to a driconf option, and add new mode.Eric Anholt
It turns out that it's not just deviceID dependent, and there's some additional undefined factor that determines the bit 6 swizzling. It's now controllable with swizzle_mode=[012] until we get a response on how to automatically detect.
2008-06-17[intel-gem] Bug #16326: Fix X tile unswizzling on 965.Eric Anholt
Apparently a bit gets flipped in the addressing for some rows of each tile.
2008-05-06[intel-GEM] Add tiling support to swrast.Keith Packard
Accessing tiled surfaces without using the fence registers requires that software deal with the address swizzling itself.
2008-01-10i965: fix segfault caused by commit e131c46b20241737ceba4856dbe01dcca6dd2c03.Xiang, Haihao
2008-01-06Simplify ctx->_NumColorDrawBuffers, _ColorDrawBuffers and fix bug 13835.Brian
These fields are no longer indexed by shader output. Now, we just have a simple array of renderbuffer pointers. If the shader writes to gl_FragData[i], send those colors to the N _ColorDrawBuffers. Otherwise, replicate the single gl_FragColor (or the fixed-function color) to the N _ColorDrawBuffers. A few more changes and simplifications can follow from this...
2007-12-12[intel] Move bufmgr back to context instead of screen, fixing glthreads.Eric Anholt
Putting the bufmgr in the screen is not thread-safe since the emit_reloc changes. It also led to a significant performance hit from pthread usage for the attempted thread-safety (up to 12% of a cpu spent on refcounting protection in single-threaded 965). The motivation had been to allow multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
2007-11-09[intel] Move over files that will be shared with 965-fbo work.Eric Anholt