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This can only happen along a malloc failure path, but check anyway.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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The pixel transfer rules state that we must set alpha to 1.0 in this case
which we can't easily do with the blitter. We can do to passes: one that
sets the alpha to 0xff and one that copies the RGB bits or we can just
use the 3D engine. Neither approach seems worth it for this case.
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Now that intel_flush() deosn't use the needs_mi_flush argument, we can
finally drop one of the two flush functions.
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With DRI2, x and y are always zero and fb->Height is always up to date
with the drawable height.
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The pitch is not really an inherent part of the miptree, since it's
not part of any of the layout calculations, and it's dictated by the
libdrm-allocated region pitch now.
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This uses a stamp mechanisms to mark the DRI drawable as invalid.
Instead of immediately updating the buffers we just bump the drawable
stamp and call out to DRI2GetBuffers "later".
"Later" used to be at LOCK_HARDWARE time, and this patch brings back
callouts at the points where we used to call LOCK_HARDWARE. A new function,
intel_prepare_render(), is called where we used to call LOCK_HARDWARE,
and if the buffers are invalid, we call out to DRI2GetBuffers there.
This lets us invalidate buffers only when notified instead of on
every glViewport() call. If the loader calls the DRI invalidate
entrypoint, we disable viewport triggered buffer invalidation.
Additionally, we can clean up the old viewport mechanism a bit,
since we can just invalidate the buffers and not worry about
reentrancy and whatnot.
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mesa core does it now. If only it did so for other entrypoints.
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Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
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* remove-intel-dri1:
intel: intelScreenContext() is no longer used
intel: Remove remaining dri2.enabled tests
intel: Drop more cliprect bookkeeping
intel: Remove struct intel_framebuffer
intel: Remove client-side vblank code
intel: Drop intelWindowMoved()
intel: Drop batchbuffer cliprect_mode tracking
intel: Drop DRI1 static regions
intel: Use depth buffer from ctx.DrawBuffer in copypix_src_region()
intel: Drop LOCK/UNLOCK_HARDWARE()
intel: Drop DRI1 SwapBuffer implementation
intel: Drop DRI1 CopySubBuffer implementation
intel: Drop DRI1 support
Push __driDriverExtensions out of dri_util.c and into the drivers
Remove leftover __DRI{screen,drawable,context}Private references
Check for libdrm_$chipset.pc when needed
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Fixes piglit fbo-copyteximage.
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As part of the DRI driver interface rewrite I merged __DRIscreenPrivate
and __DRIscreen, and likewise for __DRIdrawablePrivate and
__DRIcontextPrivate. I left typedefs in place though, to avoid renaming
all the *Private use internal to the driver. That was probably a
mistake, and it turns out a one-line find+sed combo can do the mass
rename. Better late than never.
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Use src->draw_offset intead of zero. Zero usually worked, except when
the src renderbuffer is actually a texture mipmap level higher than zero.
Fixes progs/test/blitfb.c test.
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Conflicts:
src/mesa/drivers/dri/intel/intel_fbo.c
src/mesa/drivers/dri/intel/intel_mipmap_tree.c
src/mesa/drivers/dri/intel/intel_mipmap_tree.h
src/mesa/drivers/dri/intel/intel_tex_copy.c
src/mesa/drivers/dri/intel/intel_tex_image.c
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By just using offsets, we confused the hardware's tiling calculations,
resulting in failures in miptree validation and blit clears.
Fixes piglit fbo-clearmipmap.
Bug #23552. (automatic mipmap generation)
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This lets us get rid of intel_miptree_depth_offsets() and simplify all
of the calling code.
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Conflicts:
src/gallium/auxiliary/util/u_cpu_detect.c
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Avoids an unnecessary fallback.
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Per the suggestion in the Intel driver, move the calls to
ctx->Driver.GenerateMipmap() into core Mesa so that drivers don't
have to worry about it.
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Really, we should be checking that the MesaTexFormat for the read buffer
and the texture match, but the previous code wasn't even doing that, so
matching the cpp should be an improvement (and potentially fix some hangs!).
The previous code also rejected GL_RGB even though blitting the alpha
channel to the ignored channel of an x8r8g8b8 texture should be fine, which
tripped up compiz's blur plugin.
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This is somewhat nasty, but we need to do Y-tiled depth for FBO support.
May help with corruption and hangs since enabling texture tiling, and
since switching depth textures to Y tiled.
Fixes piglit depthtex.c on 965.
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I was in the midst of fixing some blitting-with-Y-tiled issues when I
noticed this. Hopefully PBO usage will be a little more robust, as a
result.
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This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
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This prevents the width / height from being clipped to the window size before
the texture is allocated. This matches intelCopyTexImage1D.
This should fix bug #21227
Signed-off-by: Ian Romanick <ian.romanick@intel.com>
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In addition to being HW accelerated, it avoids the incorrect
(black) rendering of the mipmaps that SW was doing in fbo-generatemipmap.
Improves the performance of the mipmap generation and drawing in
fbo-generatemipmap by 30%.
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glCopyTexSubImage already gets the (correct) clipping for us, so it doesn't
need the path. While moving the clipping out, replace the code with the mesa
path to do the same job.
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The images aren't mapped at this point, so we want the generic Mesa path for
GenerateMipmapEXT that does the mapping/unmapping for us. Ideally Mesa would
just call it for us.
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There were hacks in EmitCopyBlit before to adjust offsets so that y=0 after
the offsets had been adjusted for a negative pitch. It appears that those
hacks were due to an unclear and surprising aspect of the hardware: inverting
the pitch results in the blit into the specified rectangle being inverted,
without the user needing to adjust y and base offset.
Tested with piglit copytexsubimage test on 915GM and GM965. Should fix
serious performance issues with ETQW and other applications.
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The ARB extension is a superset of the older SGIX extension. Any
hardware that can support the SGIX version can also support the ARB
version. In Mesa, any driver that supports one also supports the
other. This unification just simplifies some bits of code.
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Makefile.template
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This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
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This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
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Didn't hurt 915, but needed for 965.
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Most of these were to ensure that caches got synchronized between 2d (or meta)
rendering and later use of the target as a source, such as for texture
miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(),
which just drops an MI_FLUSH. Most of the remainder were to ensure that
REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped.
Those are now replaced by automatically flushing those when dropping the lock.
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The screen wide info such as pitch and cpp are obsoleted by the FBO
changes, so clean up the last few references to those, except for
setting up the legacy screen regions.
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