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mipmap pitches must account for the device alignment requirements, which
used to be fairly simple; just align to a 4-byte boundary. However, to allow
textures to be drawn to under TTM, they now need to be aligned to a 64-byte
boundary. Placing all of the alignment constraints in a single function
allows this new constraint to be applied uniformly.
There was some pitch constraining code in intel_miptree_create, but that was
modifying the pitch long after the miptree had been layed out, so it only
served to wreck the mipmap and cause rendering errors.
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In the process, fix some alignment issues:
- Scratch space allocation was aligned into units of 1KB, while the allocation
wanted units of bytes, so we never allocated enough space for scratch.
- GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of
ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
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which make small textures(4x4,2x2,1x1) work well.
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This seems to work now. Also fix i945 set_level_info, need to match i915
behaviour for storing mip height, as it's assumed to be the mip width
(in texels) elsewhere and the division by 4 is done later (untested).
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Based on a patch from Keith Whitwell, with some further fixes.
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Use the i965 version as it has some fixes over the i915tex version.
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