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Mesa requires that we be able to share objects between contexts, which means
that the objects need to be created by the same bufmgr, and the bufmgr
internally requires pthread protection for thread safety.
Rely on the bufmgr having appropriate locking.
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This interface has to be re-written to not be dumb and to work
for multiple apps.
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(Reverts a change to work around the problem on 965).
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This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
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This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
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Previously, the updated images would be ignored because the miptree in the
image matched the miptree in the object, even though Mesa core had just attached
updated contents in ->Data. Additionally, Mesa core could have tried to
free inside our miptree if it had already been validated.
Fixes bug #17077.
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(bug #16852, #16853)
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Conflicts:
src/mesa/drivers/dri/intel/intel_span.c
src/mesa/main/fbobject.c
This converts the i915 driver to use the GEM interfaces for object management.
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To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
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Effectively default to vblank_mode=3 on Intel to avoid tearing by default.
Users wanting to go "as fast as possible" (despite not being able to see frames
faster than their refresh rate allows) can still set the vblank_mode manually.
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Fixes oglconform rbGetterFuncs testcase. The span code for this mode hasn't
actually been tested.
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Conflicts:
src/mesa/drivers/dri/common/dri_bufmgr.c
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
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Previously, we would just store the data as malloced memory hanging off the
object, which would get memcpyed in at validate time. This broke an
oglconform render-to-texture test, since validate wasn't called but a miptree
was expected.
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This reverts commit 94979950e8991bd44899eb4067c3ae43449ce51e.
I've fixed it instead
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patch from Fedora. maybe someone can fix this later but for now
lets try and release Mesa so ajax can live his life and get Xorg 7.4 out.
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Accidentally pushed as part of the last commit.
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This will avoid clflushing entire buffers for small acesses, such as those
commonly used by regression tests.
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Didn't hurt 915, but needed for 965.
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This lets us avoid duplicated code for doing so, including the depthstencil
paths that aren't covered by SpanRenderStart/Finish. Those paths were
missing the span funcs setup, leading to a null dereference in the fbotexture
demo.
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Some buffer swap intel render buffer fields (pf_num_pages & vbl_pending) are
also used for page flipping, so enable the code that sets & updates them on
965. This allows buffer swaps and page flips to work on 965 and prevents hangs
in LOCK_HARDWARE in the buffer swap case due to an uninitialized vbl_pending
field.
Fixes FDO #16118.
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Bump the driver date and insert the string "GEM". When running tests,
this make it much easier to know that the right driver is being used.
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Enable support for ARB_texture_env_crossbar in the master extension
list instead of in every single device-specific list.
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Those functions rely on being able to treat the GET_PTR returned value as an
array indexed by x, but that's not the case for our tiling.
Bug #16387
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pointed out and debugged by stringfellow on #dri-devel
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The dri_bo_map()s that follow will take care of idling the hardware as needed.
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We have something similar in the X Server that covers X Server rendering, this
is the equivalent here for rendering to the front buffer. If we cared about
avoiding this at glFlush time, we could only do this when some actual
frontbuffer rendering had occurred.
Bug #16392.
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Apparently in Y mode we get bit 6 ^ bit 9. The reflect demo in 'd' mode now
displays correctly.
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The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode. Instead, guess the correct
tiling in screen setup.
Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is
32 scanlines, not 8.
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It turns out that it's not just deviceID dependent, and there's some additional
undefined factor that determines the bit 6 swizzling. It's now controllable
with swizzle_mode=[012] until we get a response on how to automatically detect.
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first level of the mipmap. fix #16210
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This was broken in the merge of 965 blit support. It tried to lock only
when things were already locked.
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Most of these were to ensure that caches got synchronized between 2d (or meta)
rendering and later use of the target as a source, such as for texture
miptree setup. Those are replaced with intel_batchbuffer_emit_mi_flush(),
which just drops an MI_FLUSH. Most of the remainder were to ensure that
REFERENCES_CLIPRECTS batchbuffers got flushed before the lock was dropped.
Those are now replaced by automatically flushing those when dropping the lock.
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Nothing would get drawn as the negative coordinates broke the rectangle
intersection code that used unsigned ints. Tested with copypix demo and
sliding the copy to the upper left.
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This disables the textured copy implementation on 965, which didn't appear
to work (mesa copypix demo, disable the blit path, move so that regions don't
overlap and textured is used, and you get garbage). If we resurrect this for
i965, I'd rather it used the 915-style metaops instead. Current metaops code
left in place so that whoever picks it up has a reference.
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