| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2007-11-30 | [intel] Move batch bo_unmap from TTM code to shared, and add more asserts. | Eric Anholt | |
| 2007-11-30 | [intel] Add failure path printfs to relocation code and some comments. | Eric Anholt | |
| 2007-11-30 | [intel] Simplify TTM relocation code by passing around bufmgr struct. | Eric Anholt | |
| 2007-11-30 | [intel] Fix the type and naming of the flags/mask args to TTM functions. | Eric Anholt | |
| The uint64_t flags (as defined by drm.h) were being used as unsigned ints in many places. | |||
| 2007-11-30 | [intel] intel_bufmgr_ttm style sanity | Eric Anholt | |
| 2007-11-26 | i915: Catch cases where not all state is emitted for a new batchbuffer. | Keith Whitwell | |
| This could lead to incorrect rendering or even lockups. | |||
| 2007-11-26 | i915: Some additional blit fixes and assertions. | Michel Dänzer | |
| 2007-11-16 | [intel] Add 965 support to shared intel_blit.c | Eric Anholt | |
| This requires that regions grow a marker of whether they are tiled or not, because fence (surface) registers are ignored by the 965 2D engine. | |||
| 2007-11-16 | [i915] Pass static region names in so debugging says more than "static region". | Eric Anholt | |
| 2007-11-16 | [intel] Move additional code to be shared from intel_context.h to intel/. | Eric Anholt | |
| 2007-11-16 | [intel] Move intel_tex.h into place, forgotten in the previous commit. | Eric Anholt | |
| 2007-11-16 | [965] Add batchbuffer decode for several more packets. | Eric Anholt | |
| 2007-11-16 | [intel] Fix typos in intel_chipset.h macros. | Eric Anholt | |
| 2007-11-16 | [i915] Add INTEL_DEBUG=sync debug flag to wait for fences after making them. | Eric Anholt | |
| 2007-11-16 | [i915] Reenable batchbuffer debug under INTEL_DEBUG=bat. | Eric Anholt | |
| 2007-11-16 | [i915] Push locking in intelClearWithTris down inside meta_draw_poly. | Eric Anholt | |
| The lock coverage and checks for cliprects were unneeded since the batchbuffer will have INTEL_BATCH_CLIPRECTS anyway. It appeared to be a leftover from intelClearWithBlit. This makes the locking requirements of i915 meta_draw_quad match i965 meta_draw_quad. | |||
| 2007-11-12 | i965: correct the opcode of XY_SETUP_BLT_CMD. fix bug #12730 | Xiang, Haihao | |
| 2007-11-09 | [i915] Remove old frontbuffer rotation hack. | Eric Anholt | |
| This was replaced in previous releases of xserver/dri/libGL by reporting the damage to the frontbuffer so that the server and driver could handle it appropriately. | |||
| 2007-11-09 | [intel] By default, output batchbuffer decode to stderr like other debug info. | Eric Anholt | |
| 2007-11-09 | [intel] Initialize a depth buffer if the visual has depth 24 but no stencil. | Eric Anholt | |
| 2007-11-09 | [intel] Move over files that will be shared with 965-fbo work. | Eric Anholt | |
| 2007-10-16 | Replace symlink generation from i915 with files in intel/ and symlinks there. | Eric Anholt | |
| 2007-10-08 | i915: Fix undefined ALIGN symbol from 77e0523fb7769df4bf43747e136b1653b2421b97. | Sergio Monteiro Basto | |
| 2007-10-04 | [965] Replace various alignment code with a shared ALIGN() macro. | Eric Anholt | |
| In the process, fix some alignment issues: - Scratch space allocation was aligned into units of 1KB, while the allocation wanted units of bytes, so we never allocated enough space for scratch. - GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1. | |||
| 2007-10-04 | Replace duplicated intel_reg.h with a shared header. | Eric Anholt | |
| 2007-09-27 | [965] Add batchbuffer dumping under INTEL_DEBUG=bat, like 915. | Eric Anholt | |
| 2007-09-27 | Revert "WIP 965 conversion to dri_bufmgr." | Eric Anholt | |
| This reverts commit b2f1aa2389473ed09170713301b042661d70a48e. Somehow I ended up with my branch's save-this-while-I-work-on-master commit actually on master. | |||
| 2007-09-27 | WIP 965 conversion to dri_bufmgr. | Eric Anholt | |
| 2007-08-10 | i965/i915tex: applying right alignment to compressed texture, | Xiang, Haihao | |
| which make small textures(4x4,2x2,1x1) work well. | |||
| 2007-05-19 | fix miptree layout (i915) for small compressed mipmaps | Roland Scheidegger | |
| This seems to work now. Also fix i945 set_level_info, need to match i915 behaviour for storing mip height, as it's assumed to be the mip width (in texels) elsewhere and the division by 4 is done later (untested). | |||
| 2006-12-14 | Fix copy-and-paste-o of my e-mail address. | Michel Dänzer | |
| 2006-12-14 | Fix some corner cases in i945_miptree_layout_2d(). | Michel Dänzer | |
| Based on a patch from Keith Whitwell, with some further fixes. | |||
| 2006-12-14 | Share code to lay out >= 945 style 2D mipmaps between i915tex and i965 drivers. | Michel Dänzer | |
| Use the i965 version as it has some fixes over the i915tex version. | |||
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index : android-x86-mesa.git | |
| Androïd/x86 port of Mesa drivers | Hugues Hiegel |
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