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The intelImage also holds a reference to the miptree, so unref that as well.
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This lets us avoid allocing new buffers for renderbuffers, finalized miptrees,
and PBO-uploaded textures when there's an unreferenced but still active one
cached, while also avoiding CPU waits for batchbuffers and CPU-uploaded
textures. The size of BOs allocated for a desktop running current GL
cairogears on i915 is cut in half with this.
Note that this means we require libdrm 2.4.5.
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Fixes mysterious failures in glean glsl1 test.
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This is a 2% win in fbo_firecube, and would avoid a sw fallback for
masked clears.
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It's done in the Mesa GLSL compiler. The only part of it that might
matter in drivers is the centroid sampling option for MSAA.
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While running conform with render-to-texture:
conform -d 33 -v 2 -t -direct
the i965 driver failed this assertion:
intel_clear.c:77: intel_clear_tris: Assertion `(mask & ~((1 << BUFFER_BACK_LEFT) | (1 << BUFFER_FRONT_LEFT) | (1 << BUFFER_DEPTH) | (1 << BUFFER_STENCIL))) == 0' failed.
The problem is that intel_clear_tris() is called by intelClear() to
clear any and all of the available color buffers, but intel_clear_tris()
actually only handles the back left and front left color buffers; so
the assertion fails as soon as you try to clear a non-standard color
buffer.
The fix is to have intelClear() only call intel_clear_tris() with
buffers that intel_clear_tris() can support. intelClear() already backs
down to _swrast_Clear() for all buffers that aren't handled explicitly.
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This involved fixing driConcatConfigs to not return const (which had made a
mess of a previous patch too).
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Everything other than "make sure the last rendering ends up visible on the
screen" doesn't need that behavior.
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Found while debugging cairo-gl.
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This is the big merge of the gallium-0.2 branch into master.
gallium-master-merge was just the staging area for it.
Both gallium-0.2 and gallium-master-merge are considered closed now.
Conflicts:
progs/demos/Makefile
src/mesa/main/state.c
src/mesa/main/texenvprogram.c
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Add the MSAA samples array or make sure its contents are initialized.
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Fixes bad background in all the progs/glsl/ tests.
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(cherry picked from commit f7d80aa00611917bc8ce637136d982b151b8f44f)
This also involved adding the new MSAA fields to driCreateConfigs().
Also, re-add prog_instructions->Sampler field for i965 driver. Will
have to revisit that.
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The MI opcodes have different variable length masks, so use an operand
specific mask to decode the length.
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A couple of minor typos that proclaimed an error in the wrong command, and
failed to offset the mask.
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By selecting a 4444 texture format due to a bad test, we hit the
intel_update_wrapper error path, and despite the appearance of error handling
in it and its callers, the desired behavior (software fallback) doesn't occur.
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Too much commit -a while debugging.
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No real-world impact on performance seen. Even glxgears seems to be, if
anything, happier.
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This still leaves us with a broken depth 32 visual, but now it's the server's
visual setup that's at fault.
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This is a 10% win on the ever-important glxgears not-a-benchmark.
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This saves an inadvertent round-trip to the X Server on DrawBuffers, which was
hurting some metaops.
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We can support any combination of (a8r8g8b8, x8r8g8b8, r5g6b5) x (z0,z24,z24s8)
on either class of chipsets. The only restriction is no mixing bpp when also
mixing tiling. This shouldn't be occurring currently.
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Move the remaining extension string enables to intel_extensions.c.
Make sure that GL_NV_texture_env_combine4 is not enabled on i830.
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Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
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If the texture swizzle is not XYZW (no-op) add an extra MOV instruction
after the TEX instruction to rearrange the components.
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A step toward consolidating i915/intel_state.c and i965/intel_state.c
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intel_meta_set_passthrough_transform(), intel_meta_restore_transform()
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