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These fields are no longer indexed by shader output. Now, we just have
a simple array of renderbuffer pointers.
If the shader writes to gl_FragData[i], send those colors to the N
_ColorDrawBuffers. Otherwise, replicate the single gl_FragColor (or
the fixed-function color) to the N _ColorDrawBuffers.
A few more changes and simplifications can follow from this...
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By avoiding the repeated relocation buffer creation/map/unmap/destroy for each
new batch buffer, this improves OpenArena framerates by 30%. Caching batch
buffers themselves doesn't appear to be a significant performance win over
this change.
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We have two consumers of relocations. One is static state buffers, which
want the same relocation every time. The other is the batchbuffer, which gets
thrown out immediately after submit. This lets us reduce repeated computation
for static state buffers, and clean up the code by moving relocations nearer
to where the state buffer is computed.
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This reverts commit 8bb9ae3693362a302206255c61f512d942df9bbf.
Validating our kernel buffers with the caching off in flags but on in mask
means that the kernel migrates the buffer to be uncached, which is undesired.
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The 'mask' value used in the validation operation specifies which of the
'flags' bits are being modified. Buffer validation wants to pass the memory
type and access mode (rwx) to the kernel so that the buffer will be placed
correctly, and so that the right kind of fence will be created (read vs
write). That means we actually want a constant mask for these operations,
and not something computed from the bits coming in. The constant we want is
DRM_BO_MASK_MEM | DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE | DRM_BO_FLAG_EXE.
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In order to optimize DrawPixels, the i915 texenv program isn't
applied to swrast DrawPixels in the i915 driver. This causes this
program isn't applied to any following swrast functions. Resetting
the swrast state fixes this issue. Fix #13614
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To do so, merge the remainnig necessary code from the buffers, blit, span, and
screen code to shared, and replace it with those.
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The core problem was that _mesa_generate_mipmap was not respecting RowStride
of the source image. Additionally, the intel private data associated with the
images (level and face) was not being initialized for the
_mesa_generate_mipmap-generated images.
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The 965 driver relies on flag checking instead of these hooks, and will be
using this code soon.
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Otherwise, we may violate cliprect asssertions on clearing the buffers, which
isn't affected by the fallback.
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The diffuse color format is always ARGB32, regardless of the destination
surface format.
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mipmap pitches must account for the device alignment requirements, which
used to be fairly simple; just align to a 4-byte boundary. However, to allow
textures to be drawn to under TTM, they now need to be aligned to a 64-byte
boundary. Placing all of the alignment constraints in a single function
allows this new constraint to be applied uniformly.
There was some pitch constraining code in intel_miptree_create, but that was
modifying the pitch long after the miptree had been layed out, so it only
served to wreck the mipmap and cause rendering errors.
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Don't dereference NULL renderbuffer pointer, and make sure the software
fallback sticks.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=13694 .
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This removes the delayed texture upload optimization from 965, in exchange for
bringing us closer to PBO support. It also disables SGIS_generate_mipmap,
which didn't seem to be working before anyway, according to the lodbias demo.
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965 gains fixed TTM typing of the buffer object buffers and unused PBO
functions, and 915 gains buffer size == 0 fixes from 965.
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This adds (so far) unused PBO functions, and holding the lock while writing
to regions (which may be shared static screen regions).
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The idling it was trying to ensure was covered by the
intel_miptree_image_map()->intel_region_map() that immediately followed it.
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Each buffer object now has a relocation buffer pointer, which contains the
relocations for the buffer if there are any. At the point where we have to
create a new type of relocation entry, we can change the code over to allowing
multiple relocation lists, but trying to anticipate what that'll look like
now just increases complexity.
This is a 30% performance improvement on 965.
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Now that the dri_bufmgr is stored in the context rather than the screen, all
access to one is single-threaded anyway.
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I broke this with cherry-pick resolving on
93c98a466947570e0589b662df49095b2f4bc43c.
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Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes. It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965). The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
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This takes advantage of the DRM_BO_HINT_PRESUMED_OFFSET change and allows
the kernel to avoid mapping and re-writing buffers when relocations occur.
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This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
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The uint64_t flags (as defined by drm.h) were being used as unsigned ints in
many places.
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This could lead to incorrect rendering or even lockups.
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This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
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