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This doesn't remove software TCL path - so RS480 and RS690 work as before.
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We don't have check which attributes are used by fragment program - it's already done by NQSSADCE.
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Rewrite vertex and fragment programs so that we don't have to do any hacks on lower level.
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If GL context had e.g. tex0, tex2 and fog the VAPOutputCntl1 returned 0x104 instead of 0x124 - that meaned we're sending only 8 texcoords (instead of 12) which ended up in GPU hang.
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Sending from VAP more texture coordinates than RS expects results in GPU hang.
Fixes BumpSelfShadow from DirectX8 SDK.
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software TCL path
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- move vertex program related functions to r300_vertprog.c
- use _mesa_bitcount instead of self-made bit_count function
- remove duplicated field in r300_vertex_shader_fragment.body union
- rename r300_vertex_shader_fragment to r300_vertex_shader_hw_code
- rename r300_vertex_program field native to error
- remove unnecessary r300_vertex_shader_state structure
- remove unused r300_vertex_program and r300_vertex_program_cont fields
- remove disabled code
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- move extensions init into seperate function
- move options handling into seperate function
- create new structure to hold options values
- use context->options.hw_tcl_enabled field instead of global hw_tcl_on and future_hw_tcl_on variables
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- remove unused fields
- remove unused defines and macros
- flatten one structure
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HW TCL path currently assumed fog, WPOS order. The order was inverted for SW TCL path.
This hopefully fixes rest of fog and WPOS related bugs.
Additionally fix some indentation, don't route unnecessary components of fog coordinates for performance reasons and simplify vertex
attribute emitting for SW TCL path.
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This fixes up the buffer validation scheme, so that we keep a list
of buffers to validate so cmdbuf flushes during a pipeline get
all the buffers revalidated on the next emit.
This also fixes radeonFlush to not flush unless we have something
useful to send to the GPU, like a DMA buffer or something not state
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Context destruction was nearly the same over all the drivers,
so collapse it down.
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Conflicts:
src/mesa/drivers/dri/r300/r300_cmdbuf.c
src/mesa/drivers/dri/r300/r300_state.c
src/mesa/drivers/dri/r300/r300_swtcl.c
src/mesa/drivers/dri/r300/radeon_ioctl.c
src/mesa/drivers/dri/radeon/radeon_screen.c
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Also cleanup sw tcl vertex buffer setup
Signed-off-by: Nicolai Haehnle <nhaehnle@gmail.com>
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This merges lots of the hw state atom emission and firevertices code.
it also removes a lot of the extra radeon crap from r300
and merge scissor
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this gets back a lot of the lots speed in gears on r500 at least
I also fixed the legacy bufmgr to deal when the dma space fills up
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If DRI2 is enabled then switch cmd assembly to directly build
hw packet.
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This abstract memory management and command stream building so we
can use different backend either legacy one which use old pathway
or a new one like with a new memory manager. This works was done by :
Nicolai Haehnle
Dave Airlie
Jerome Glisse
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Makefile.template
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This gets non-tcl cards working again on this branch..
at least texrect and glxgears
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Corrects commit 74ae5a875d6b3f1ffea2ac09c6ef0062d4980f15.
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finally add some information to R300_RB3D_DSTCACHE_CTLSTAT
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This patch tries to get the Z-Buffer register names in sync with the AMD spec
so that talking to AMD engineers is much simpler.
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this is correct, there is another issue with sw fallbacks
This reverts commit cc50edbca2fd3111f9987d4117fa6656599d79dc.
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I've no idea why I added this so I'll have to spend time tracking it down
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See the conversation between myself and Tommy Schultz Lassen on mesa3d-dev.
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Apparently for back facing color to work you must set all 3 color bits; I guess
the hardware cannot handle them separately.
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makes gears work with swtcl
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According to the comment you do not need to setup INPUT_CNTL when using vertex
buffers. However, not doing so results in a lockup.
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