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Noticed by pzad on IRC
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The PVS_VECTOR_OPCODE macro should be modified to support macro instructions,
too.
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This opcode is likely a mistake from reverse engineering. MAD_2 isn't included
in AMD's documentation, and my testing reviles there is no problem using the
documented MAD opcode.
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These changes are taken from the xf86-video-ati driver. They update the header
file accordingly and also remove some UNKOWN variables.
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This commit adds most of the graphics backend registers and of the rasterizer
registers. Again, some minor bugs were found and marked with TODO or even
fixed.
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handling)
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finally add some information to R300_RB3D_DSTCACHE_CTLSTAT
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RB3D_COLOR_CHANNEL_MASK
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This patch tries to get the Z-Buffer register names in sync with the AMD spec
so that talking to AMD engineers is much simpler.
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I've no idea if this code might break something or how it should interact
with vertex shaders, it makes the clip demo work for me
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Possibly performance may improve by setting it to the last instruction that
writes result.position, rather than the last instruction in the vertex program.
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