Age | Commit message (Collapse) | Author |
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Possibly performance may improve by setting it to the last instruction that
writes result.position, rather than the last instruction in the vertex program.
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These registers are per-pixel and per-vertex X and Y clipping planes.
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I haven't converted all of the Type 3 packets to the CP_PACKET3 macro yet
because some of the Type 3 packet defines are missing from the R300 register
definition file.
These defines need to be copied from DRM and Mesa into the R300 register
definition file then copied into both DRM and Mesa.
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This reverts commit bb3558e6517209086cf8426bbe4743da50351158.
This commit caused a regression reported by Markus Amsler
<markus.amsler@oribi.org>. Apparently these defines are required, although I'm
not sure why.
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Supposedly you need to set these values for the interpolaters to work, but they
seem to work fine without these values.
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There used to be an assertion when a fragment program accesses an incomplete
texture image. Work around this assertion.
Note: I am unsure whether this workaround produces the desired result
(0,0,0,1) on all hardware.
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There were a number of bugs related to the pairing of vector and scalar
operations where swizzles ended up using the wrong source register,
or an instruction was moved forward and ended up overwriting an aliased
register.
The new algorithm for register allocation is quite conservative and may
run out of registers before necessary. On the plus side, It Just Works.
Pairing is done whenever possible, and in more cases than before, so
in practice this change should be a net win.
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enough information is known about them to be sure as to what the values mean.
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Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
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(Oliver McFadden)
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This need more work on case where we can disable
or enable early (stencil, alpha might need it to
be disable).
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CMPH a0, a1, a2 -> if a2 > 0.5 return a1 else return a0
Guessed by examinating LIT instruction handling of FGLRX.
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and fixing a couple of warning. More cleanup and shuffle
to come. I have tested this change they might broke things
especialy with r300_texstate.c change (format_x doesn't
seems to be use at all by r300).
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known by ddx (probably secondary ids, non-existant cards and similar). Add rs400 to the family enum, and configure the rv410 like a 2 quad chip (?)
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Lots of changes, and fixes for some badness on my behalf.
1. Disposable data used during fp compile is now per-context,
rather than per-program to save memory.
2. Track usage of INPUT/TEMP registers from Mesa program, free
them when no longer required so the hw temps can be re-used.
3. Changed LAST_NODE to OUTPUT_COLOR (see r300_reg.h)
4. Implemented remaining ARB_f_p instructions, with the exception
of the trig/LIT opcodes.
5. Treat ZERO/ONE swizzles the same way as other native swizzles.
6. emit_arith changes, basically a complete re-write. Should
produce cleaner instructions, but no real functional changes.
internal reg -> hw reg routines shared with emit_tex. A bit
messy still.
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sw tcl
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Changes to current operation:
-Elts are no longer converted to 16-bit format
-Cube maps
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- Calculate tc_count in EmitArrays (enabled units != nr texcoords).
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- Handle REPL_ALPHA in emit_arith (possibly incorrect for some things)
- Start on getting demos/arbfplight.c to look right. Won't be animated yet,
need to re-work const emit so we can update consts without re-translating
the entire program.
Assertion in r300_state.c::setup_rs_unit needs to be disabled for it to
work.
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generation in Mesa. Requires most recent Mesa cvs to work correctly.
Swizzle code is possibly slow/buggy and will probably be replaced.
Old behaviour can be controlled by a #define in r300_context.h, if
no-one minds I'll remove the old code later on.
Also, disabled cube map extension. AFAIK We don't support it yet,
and it causes issues with UT2004.
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