| Age | Commit message (Collapse) | Author |
|---|
|
|
|
|
|
|
|
|
|
All rendering is checked in r300PredictTryDrawPrimsSize which mamde these calls useless.
|
|
Trying to make understanding code easier with small refactoring and renaming.
|
|
|
|
We do flush for cmd buffer in case there isn't enough space left for whole
rendering operation. This protects dma regions from getting released in middle
of state emit.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
|
|
|
|
This makes it easier to predict size of next rendering operation so we
can do early flush.
|
|
This fixes some state atom check functions from returing wrong emit size.
There is emit code cleanup so that emit function selection is done in init
time instead of runtime.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
|
|
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
|
|
We keep dma buffer objects in list untill they have been unused for many
draw operations. Current limit of having 100 flushes is just guess for
good performance/memory trade off.
Moving WARN_ONCE macro to common context because it is used in multiple drivers.
Signed-off-by: Pauli Nieminen <suokkos@gmail.com>
|
|
|
|
|
|
Move to common code base so radeon/r200 can add support for this.
Make OQ start a state emitted like all normal state, and make no-tcl
flushing work in proper places.
Really need a generic post emit space reservation mechanism like max_state
so we can reserve some space for the emit
this code passes demos/arbocclude, piglit occlusion query and
glean occlusion query with TCL and NO-TCL on my rv530.
|
|
|
|
|
|
Split vbo rendering when the number of elements requested
by drawarrays is bigger than 65536.
|
|
|
|
Supported only on HW with TCL block and with proper radeon drm.
Required minimum radeon drm version is 1.30 or KMS.
|
|
|
|
|
|
|
|
TODO:
- use proper interface for checking if bo is idle when it's available
- disable ZTOP only when needed
- make it work under KMS
|
|
Hopefully this gets the ordering correct so the space checks don't fail.
|
|
|
|
Based on Maciej's code, just fixed up the alignments for INDX_BUFFER
ut2004 runs AS-Convoy
|
|
Conflicts:
src/mesa/drivers/dri/r300/r300_draw.c
|
|
|
|
|
|
Revert to previous behaviour of dropping to big render operations.
|
|
Copy elements directly to DMA bo to get rid of one memcpy, and prepare for using VBOs for index buffer.
|
|
This doesn't remove software TCL path - so RS480 and RS690 work as before.
|
|
|
|
Reported by adamk on #radeon
|
|
|
|
This saves mapping the index buffer to get a bounds on the indices that
drivers just drop on the floor in the VBO case (cache win), saves a bonus
walk of the indices in the CheckArrayBounds case, and other miscellaneous
validation. On intel it's a particularly a large win (50-100% in my app)
because even though we let the indices stay in both CPU and GPU caches, we
still end up waiting for the GPU to be done with the buffer before reading
from it.
Drivers that want the min/max_index fields must now check index_bounds_valid
and use vbo_get_minmax_index before using them.
|
|
The regression was introduced by 9a1c336253579d8b58b31910325227b22b4af395
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
|
|
R300 hardware (but _not_ R500) hardware requires an enabled texture unit
if KIL is used in fragment programs. We now work around the CS checker
correctly when enabling such a fake texture unit.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
|
|
We used to not always correctly re-emit the Z buffer size in all cases,
in particular the clear path, and invalidated state was not always picked
up correctly.
This fixes a bug where the kernel CS checker correctly complains about
a Z buffer that is too small.
Note that this bug was probably only visible with ridiculously high
framerates, i.e. glxgears.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
|
|
This almost fixes compressed mipmapped textures on r200, though some small
mip levels are still broken.
Leave r300 compressed texture stride as is though afaik it's different
to pre-radeon-rewrite too. Also do the fixup for rs600 uncompressed row stride
at same place.
|
|
The field is not used, and in any case it would be more interesting to
manipulate from *outside* the compiler if we ever wanted to load several
fragment programs at the same time or something.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
|
|
Configuration register values are now stored directly in that structure.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
|
|
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
|
|
In the long run, it's probably better to just get rid of InputsRead and
OutputsWritten.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
|
|
|
|
|
|
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
|
|
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
|
