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path: root/src/mesa/drivers/dri/r300
AgeCommit message (Collapse)Author
2008-05-19r5xx: Fixup emit_tex, add debugging info, enable temp temps.Corbin Simpson
emit_tex now chases itself with an OUT if needed. Added airlied's dump_program, with some fixes.
2008-05-19r500: add more input srcsDave Airlie
2008-05-19r500: fix swz gets and some returnsDave Airlie
2008-05-19r500: add mask debuggingDave Airlie
2008-05-19r500: add fragment program debug dumperDave Airlie
2008-05-19r5xx: Fix magic offsets for output fifo write masks.Corbin Simpson
Well, this sure explains a lot.
2008-05-18r5xx: Swap sources for CMP.Corbin Simpson
Follows the same pattern as the op on r3xx/r4xx. Thanks airlied.
2008-05-18r5xx: Fix typo of epic proportions.Corbin Simpson
2008-05-18r5xx: ALU/OUT fixups.Corbin Simpson
Lots of small changes. Intentionally breaks some tex stuffs.
2008-05-18r300: fixup US_OUT_FMT bitsDave Airlie
2008-05-18r500: you can have a single texcoordDave Airlie
2008-05-17r5xx: Add OPCODE_KIL.Corbin Simpson
2008-05-17r5xx: Added OPCODE_DPH.Corbin Simpson
Like DP4, but with one swizzle change.
2008-05-17r5xx: Fix FRC.Corbin Simpson
This makes tri-frc work. (Remind me again why I'm allowed near a compiler, lawl.)
2008-05-17r5xx: Fix SCS.Corbin Simpson
Output instructions need to be marked OUT so they can write to the fifo. Also, negation doesn't work with SWZ yet.
2008-05-17r5xx: Add OPCODE_SWZ.Corbin Simpson
It's so easy!
2008-05-17r5xx: Add OPCODE_SCS.Corbin Simpson
It's disabled, though, because it doesn't work. I'll figure it out later...
2008-05-17r5xx: Adding more opcodes.Corbin Simpson
EX2, FRC, LG2, SIN, RCP, and RSQ, if you care. All of these except FRC are like COS. This pretty much rounds out the set of opcodes which can be done in one ALU inst.
2008-05-17r5xx: First swing at OPCODE_COS.Corbin Simpson
2008-05-17r5xx: Unbreak MAX and MIN.Corbin Simpson
Both of them had faulty copypasta.
2008-05-17r500: set fragprog end to correct placeDave Airlie
2008-05-17r300: SC register naming cleanupAlex Deucher
2008-05-17r500: write out the correct FP registersAlex Deucher
2008-05-15r500: default rsunit swizzle like fglrxDave Airlie
2008-05-15r500: shift tex src properlyDave Airlie
2008-05-15r500: fixup r500 rs unit texture coordinate countingDave Airlie
2008-05-15r500: remove some debuggingDave Airlie
2008-05-15r500: split output/pixel masks and emit in the correct placesDave Airlie
2008-05-15r3/500: emit RS state before VAPDave Airlie
2008-05-15r500: fixup the program allocations to be the correct sizesDave Airlie
2008-05-15r300: set screen so that context init can find out chip idsDave Airlie
2008-05-15r500: add cmp support in theoryDave Airlie
2008-05-15r500: some trivial fixups to get tri working.Dave Airlie
the counter was being used one instruction over the end
2008-05-15r500: we just need to emit a colour for clear drop tex instructionDave Airlie
2008-05-13R300: clean up GA registersAlex Deucher
2008-05-13R3xx: clean up ZB registersAlex Deucher
2008-05-13R300: clean up CB registersAlex Deucher
2008-05-13R300: clean up Fog registersAlex Deucher
2008-05-13R500: fixup r300EmitClearState() FP for r5xxAlex Deucher
2008-05-13R300: cleanup FS code and fill in missing detailsAlex Deucher
2008-05-13R3xx: more PVS cleanupAlex Deucher
2008-05-12Merge branch 'r500-support' of ↵Alex Deucher
git+ssh://agd5f@git.freedesktop.org/git/mesa/mesa into r500-support
2008-05-12R500: add support for 4k texturesAlex Deucher
2008-05-07r500: cleanup r500 RS setupDave Airlie
2008-05-07r500: for rectangular textures set to unscaled coordinates.Dave Airlie
2008-05-07r5xx: Fix FP inputs. (For good?)Corbin Simpson
FP inputs are now counted and mapped correctly, and temps are allocated tightly and correctly.
2008-05-06r5xx: Fix false error with DP3/DP4.Corbin Simpson
DP3/DP4 only takes two arguments, but tried to load three, causing a false fallback to the dumb shader.
2008-05-06r5xx: Index inputs and temps.Corbin Simpson
This is not the same as r3xx indexing. It only tries to protect inputs on the pixel stack from getting clobbered by temps or texs. Texs don't need special treatment since they read from special input regs and write to the same temp regs as ALU/FC instructions.
2008-05-06r5xx: FP: Add OPCODE_TXB.Corbin Simpson
Tex lookup with biased LOD. Should magically work.
2008-05-06r5xx: FP: Make MOV/ABS look pretty.Corbin Simpson
We can't really do anything like emit_alu, so we're doing emit_mov instead.
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