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random output is bad
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Stride == 0 means that we value for first vertex should be copied to every other vertices (e.g. constant color).
This fixes glean/vertProg1 and sauerbraten with enabled shaders.
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The problem is if we find out later we don't have any cmdbuf space but
we've already written the arrays to the DMA buffer object, we end up
emitting the current cmdbuf which has references to the current DMA object
we then send that to the hw and we can't reference the arrays we just emitted
to the old DMA buffer. things go bad, crash boom.
This can probably be tuned further + swtcl probably needs some fixes
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This moves a big chunk of the space checking code into libdrm so
it can be shared by the DDX.
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- don't limit vertex count if we are using indices
- max indices count is 65535 not 65536
- remove some comments that don't apply anymore
- remove unreachable code
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half stealing the code without taking the intel regions
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I suspect this might break TFP in some way but it makes firecube run here
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Add all source files that are symlink'ed from common radeon code to the
ignore list.
Signed-off-by: Nicolai Hähnle <nhaehnle@gmail.com>
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still always enable max, but the right values this time.
More work should probably be done for saner limits without mm, and/or
dri conf option allow_large_textures (which is ignored) removed.
3D limit on r100 is pretty arbitrary as still handled by swrast anyway.
Also fix r300 limits (except 3d I've no idea what the max is anyway so
keep using mesa default).
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Conflicts:
src/mesa/drivers/dri/i915/i915_tex_layout.c
src/mesa/drivers/dri/i965/brw_wm_glsl.c
src/mesa/drivers/dri/intel/intel_buffer_objects.c
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c
src/mesa/drivers/dri/intel/intel_pixel_draw.c
src/mesa/main/enums.c
src/mesa/main/texstate.c
src/mesa/vbo/vbo_exec_array.c
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Fixes #22181. R200 requires this since DP4 is used in hw tnl mode.
R300 prefers it (should be faster due to no instruction dependencies), but
both methods should be correct (when sw tcl is used though, MUL/MAD might
be faster). Probably doesn't make much difference for R100 since vertex progs
are executed in software anyway, but let's just keep it the same there too.
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Fixes #22181. R200 requires this since DP4 is used in hw tnl mode.
R300 prefers it (should be faster due to no instruction dependencies), but
both methods should be correct (when sw tcl is used though, MUL/MAD might
be faster). Probably doesn't make much difference for R100 since vertex progs
are executed in software anyway, but let's just keep it the same there too.
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This lets ut2004 avoid hitting the elt warning.
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vap index offset is programmed to 0 by the kernel, it
would add work to kernel checker to allow userspace
programming of this so it's now disallowed with CS
on KMS.
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Tested with glean/texture_srgb and wine/d3d9 tests on RV535
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use the actual value set in the context
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If GL context had e.g. tex0, tex2 and fog the VAPOutputCntl1 returned 0x104 instead of 0x124 - that meaned we're sending only 8 texcoords (instead of 12) which ended up in GPU hang.
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We shouldn't use i variable for SWTCL_OVM_TEX because textures doesn't have to be enabled in "packed" order.
We could have tex1,tex3 and fog which would receive 7,9,8 OVM locations instead of 6,7,8.
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RS_COL_FMT field is part of RS_IP_* reg not RS_INST_*
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- when rewriting per component negate swizzle, first instruction should get not negated source
- KIL instruction ignores swizzles
TODO:
- tex instructions does not support saturation
- tex instructions cannot read from consant memory
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Sending from VAP more texture coordinates than RS expects results in GPU hang.
Fixes BumpSelfShadow from DirectX8 SDK.
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If the vertex program didn't write position attribute, the position invariant function would add necessary instructions, but the vertex position would be overwritten by artificial outputs insts added to satisfy fragment program requirements.
Fixes "whole screen is gray" problem for HW TCL path in sauerbraten when shaders are enabled, and whole slew of wine d3d9 tests.
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If the vertex program wrote secondary color without primary color, the secondary color output register index would be 0 which resulted in overwriting vertex position in some cases.
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vertices
When with memory manager we need to make sure the GPU won't try to access
beyond vertex buffer size, do so by enforcing that the maximun index is the
last vertex of the buffer.
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Fixes GPU hangs in software TCL path
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Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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Also when index format is GL_UBYTE, convert it to GL_USHORT not GL_UINT.
Fix license header too.
Reported by: Nicolai Hähnle <nhaehnle@gmail.com>
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software TCL path
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Always allocate the vertex program input registers in the same order as the vertex attributes are passed in vertex arrays.
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Even if we don't pass all 4 color components to vertex shader unit, the vertex program can generate the missing components.
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