Age | Commit message (Collapse) | Author |
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3 more piglits, cool.
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The variable loops would be used uninitialized if it ever processed a
RC_OPCODE_ENDLOOP case first.
This patch initalizes the loops variable to NULL and adds an assert at
the RC_OPCODE_ENDLOOP case that loops isn't NULL.
Silence the following GCC warning.
r3xx_vertprog.c: In function 'translate_vertex_program':
r3xx_vertprog.c:469: warning: 'loops' may be used uninitialized in this function
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This is a follow-on patch to commit
574ba4b5f50bfe661427327cd792a8a200559376.
Fixes r300g SCons build.
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Wine likes to create a *lot* of constants, exceeding the size of the constant
file in hw.
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Also rename "compiler" to "c".
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i.e. relative addressing (mainly FS), saturate modifiers, exceeding
the maximum number of constants.
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If there is relative addressing of temporaries, we cannot change register
indices, so skip register allocation entirely. To utilize register allocation
at least partially, we need separate indexable and non-indexable register
files in both TGSI and Mesa IR.
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Single loops work, but nested loops do not.
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This can be supported on r600 without using the endian swapper, and is a
better fit for (typical) uploads using GL_BGRA, GL_UNSIGNED_INT_8_8_8_8_REV
anyway.
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Fixes a hardlock.
NOTE: this is a candidate for the 7.8 branch, provided the half float vertex
is really implemented there.
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The BGNLOOP and ENDLOOP instructions are now being used correctly, which
makes break and continue possible. The deadcode pass has been modified to
handle breaks, and the compiler is more careful about which loops are
unrolled.
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When a DRI2 swap buffer is pending we need to make sure we
have the flush extension so radeon doesn't resume rendering to
or reading from the not yet blitted front buffer.
This fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=28341
https://bugs.freedesktop.org/show_bug.cgi?id=28410
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
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This reverts commit 8446f257b3e3ca4a3eb2c79bc357e46343e04e87.
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When DRI2 swap buffer is pending (copy buffer not pageflipping)
we need to make sure we have the flush extension so radeon doesn't
resume rendering on the not yet blitted front buffer.
Modified version of Jerome's patch to add flush extension
in the correct place.
This prepares a possible fix for:
https://bugs.freedesktop.org/show_bug.cgi?id=28341
https://bugs.freedesktop.org/show_bug.cgi?id=28410
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
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Despite the docs, the corresponding hardware instructions are r5xx-only.
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Candidate for 7.8 branch
Signed-off-by: Maciej Cencora <m.cencora@gmail.com>
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This pass renames register in order to make it easier for the pair
scheduler to group TEX instructions together.
This fixes fdo bug #28606
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The following instruction sequence will no longer be emitted in separate
TEX blocks:
0: TEX temp[0].xyz, temp[1].xy__, 2D[0];
1: TEX temp[1].xyz, temp[2].xy__, 2D[0];
This fixes fdo bug #25109
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Signed-off-by: Marek Olšák <maraeo@gmail.com>
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block.
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This also allows us to split the loop emulation into two phases. A
tranformation phase which either unrolls loops or prepares them to be
emulated, and the emulation phase which unrolls remaining loops until the
instruction limit is reached. The second phase is completed after the
deadcode analysis in order to get a more accurate count of the number of
instructions in the body of loops.
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1. Move all GL entrypoint functions and files into src/mesa/main/
This includes the ARB vp/vp, NV vp/fp, ATI fragshader and GLSL bits
that were in src/mesa/shader/
2. Move src/mesa/shader/slang/ to src/mesa/slang/ to reduce the tree depth
3. Rename src/mesa/shader/ to src/mesa/program/ since all the
remaining files are concerned with GPU programs.
4. Misc code refactoring. In particular, I got rid of most of the
GLSL-related ctx->Driver hook functions. None of the drivers used
them.
Conflicts:
src/mesa/drivers/dri/i965/brw_context.c
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It is not perfect, but it is the best we got.
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