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fixes fdo bug 27043
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Check if the native blit formats are supported, if not,
attempt to use an alternate format.
Skip 3, >4 bpp as per comments from mcencora on irc.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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This hides the assertion failure in glean/fbo test. Underlying
problem when same texture is set twice to different attachments
will cause assertion.
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Fixes glActiveTexture to set GL_INVALID_ENUM when trying
to activate texture unit that is not available.
piglit test case general/texunit passes now.
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also clarify some other const values.
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* remove-intel-dri1:
intel: intelScreenContext() is no longer used
intel: Remove remaining dri2.enabled tests
intel: Drop more cliprect bookkeeping
intel: Remove struct intel_framebuffer
intel: Remove client-side vblank code
intel: Drop intelWindowMoved()
intel: Drop batchbuffer cliprect_mode tracking
intel: Drop DRI1 static regions
intel: Use depth buffer from ctx.DrawBuffer in copypix_src_region()
intel: Drop LOCK/UNLOCK_HARDWARE()
intel: Drop DRI1 SwapBuffer implementation
intel: Drop DRI1 CopySubBuffer implementation
intel: Drop DRI1 support
Push __driDriverExtensions out of dri_util.c and into the drivers
Remove leftover __DRI{screen,drawable,context}Private references
Check for libdrm_$chipset.pc when needed
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As part of the DRI driver interface rewrite I merged __DRIscreenPrivate
and __DRIscreen, and likewise for __DRIdrawablePrivate and
__DRIcontextPrivate. I left typedefs in place though, to avoid renaming
all the *Private use internal to the driver. That was probably a
mistake, and it turns out a one-line find+sed combo can do the mass
rename. Better late than never.
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This makes the miptree rounds up to the near POT for each level for
all radeons, however since mipmaps aren't support with NPOT on previous
radeons this calculation shouldn't cause any problems. If it does
we can just make it r600 only.
I tested a few mipmap demos on r500 and they all seem to work.
Signed-off-by: Dave Airlie <airlied@redhat.com>
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R600_ENABLE_GLSL_TEST defined, IL shader code will goto r600 assembler.
The test base is /mesa/progs/glsl/brick, and changes
shader code in CH06-brick.frag/vert to test different logic op
combination. (if,else,while,function,...). The stack depth code is not
in yet, so it is hard coded now. So complex code would not run (such as
things like 8 loops embeded loop in loop).
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Based on initial patch from Stephan Schmid <stephan_2303@gmx.de>.
Basic idea is to dump the zpass count at the start and end of the query
and subtract to get the total number of visible fragments. HW writes
alternating qwords for up to 4 DBs. On the first pass, we start at
buffer address + 0; on the second pass, we start at buffer address + 8
(bytes). The resulting buffer at the end of the query looks like:
qw[0]: db0 start
qw[1]: db0 end
...
qw[6]: db3 start
qw[7]: db3 end
The MSB of each qword is the valid bit and the lower 63 bits are
the zpass count for that DB.
OQ on RV740 is disabled at the moment as it only seems to report
results for half of its DBs. This needs further investigation.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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This enables the remap table in core. driInitExtensions is adapted to
use the remap table. All uses of extension_helper.h are replaced by
remap_helper.h. The chicken-egg problem of the DRI drivers is also
solved.
It is now also possible to pass NULL extensions to driInitExtensions.
It will cause driInitExtensions to map all known functions. This
functionality is used by software drivers and EGL_i915.
Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
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Make it more consistent with other radeon drivers.
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128 gprs, 256 reg-based consts
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- max texture size is 8k, but mesa doesn't support
that at the moment.
- attempt to set shader limits to what the hw actually
supports
- clean up some old r300 cruft
- no need to explicitly disable irqs. This is fixed
in the drm now.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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I inherited this and really it stayed around far too long,
make it nice and simple.
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There is only a few functions that have debugging enabled now.
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Not doing so seems to cause lock-ups or rendering problems
on some chips. I think there is an logic issue related to
CB and VGT on some chips. We ran into similar issues in
r600_demo IIRC.
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We probably want to go finer grained eventually, but
this is a good start.
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texture bo setup isn't quite working yet
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