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path: root/src/mesa/drivers/dri/r600/r700_assembler.c
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2010-09-13r600c: eg: fix typoAndre Maasikas
probably copy/paste error
2010-09-09r600: add TXL instruction and note about TXBAndre Maasikas
2010-09-09r600: remove depth exports move, just set to output x <- z in the export ↵Andre Maasikas
intruction
2010-09-09r600: protect cleanup instructions from double freeAndre Maasikas
We might get the cleanup when we have not translated the shader yet e.g 2 programstringnotifys in a row
2010-09-09r600: remove mask from output intructionsAndre Maasikas
in case of relative addressing we never get to know which comps were really written.
2010-09-09r600: allow relative addressing of temps, inputs, outputsAndre Maasikas
2010-09-09r600: handle LIT writemaskAndre Maasikas
2010-09-09r600: fix rsq from negative inputAndre Maasikas
arbfp specifies rsq of abs value
2010-08-29evergreen : fix shader const allocation and instruction bugs.Richard Li
2010-08-20evergreen : initial support driver code.richard
2010-08-18r600: implement SSG instructionAndre Maasikas
2010-08-18r600: implement DP2 opcodeAndre Maasikas
2010-08-17r600c: Handle reads from PROGRAM_OUTPUTHenri Verbeet
with glsl2, reads from outputs are legal
2010-08-04r600: relax stride/alignment requirements for verticesAndre Maasikas
seems hw can do unaligned accesses and unaligned strides removes extra conversion when using vbo's however I needed to switch 3 component byte format to 4 component formats for tests to pass. Somewhat sililar to GL_SHORT fix done earlier removes assert and gains +2 piglit especially draw-vertices
2010-08-02r600: fix sin,cos functions on r600Andre Maasikas
r600 doesnt need the same normalization as r700 - instead it requires range to be truncated to -pi..pi I left the range trunc also effective on r700 althouch according the docs it has sufficent range (-512*PI, +512*PI). The instructions seem to be used not too often to cause perf loss because of this Based on patches and testing by Conn Clark and Alain Perrot
2010-07-29r600: since 8744c36e added asserts - use another random register for shader ↵Andre Maasikas
with no output
2010-07-15r600: fix typo in r700 assemblerAlex Deucher
Noticed by Henri Verbeet on IRC. NOTE: This is a candidate for the 7.8 branch.
2010-07-07r600: workaround 3 comp GL_SHORT vertex attribute format on r700Andre Maasikas
guess it's a hw errata?
2010-06-23Merge branch 'shader-file-reorg'Brian Paul
1. Move all GL entrypoint functions and files into src/mesa/main/ This includes the ARB vp/vp, NV vp/fp, ATI fragshader and GLSL bits that were in src/mesa/shader/ 2. Move src/mesa/shader/slang/ to src/mesa/slang/ to reduce the tree depth 3. Rename src/mesa/shader/ to src/mesa/program/ since all the remaining files are concerned with GPU programs. 4. Misc code refactoring. In particular, I got rid of most of the GLSL-related ctx->Driver hook functions. None of the drivers used them. Conflicts: src/mesa/drivers/dri/i965/brw_context.c
2010-06-16r600: fix warningsMarc
2010-06-10mesa: rename src/mesa/shader/ to src/mesa/program/Brian Paul
2010-06-08r600: Make next_inst() static.Henri Verbeet
2010-06-08r600: Assert output registers have a valid export index.Henri Verbeet
2010-06-08r600: Process exports for all written fragment outputs.Henri Verbeet
2010-04-26r600: enable VERT_RESULT_PSIZ - makes point size & attenuation workAndre Maasikas
doc additions: shader export ARRAY_BASE for EXPORT_POS: 60 is position, 61 is misc vec(VS_OUT_MISC_VEC - used here), 62, 63 are clip distance vectors(VS_OUT_CCDIST#) sorry for formating - there seem to be so many different styles in r600
2010-02-27r600: Assert pointer is not null before dereferencing.Vinson Lee
2010-02-24r600: Assert that array index is not negative.Vinson Lee
2010-02-14r600: Silence uninitialized variable warnings.Vinson Lee
2010-02-14r600: Silence uninitialized variable warning.Vinson Lee
2010-01-27r600: fix XPD with writemaskAndre Maasikas
same variable used for 2 different temp registers fixes e.g. glsl/bump
2010-01-18r600: fix some warningsAlex Deucher
2010-01-18r600: fix shadow_ambient shaderAndre Maasikas
rtype enums are different, DST_REG_OUTPUT got SRC_REG_CONSTANT in some shaders and produced invalid output/hang as TEX output is temp register always set out src to SRC_REG_TEMPORARY
2010-01-05r600: support depth compare functions & shadow_ambientAndre Maasikas
2010-01-04r600: support vertex_array_bgraAndre Maasikas
Use vertex program key mechanism and swizzle during vertex fetch - is there a better way?
2009-12-22mesa: adjust OPCODE_IF/ELSE BranchTarget fields to point to ELSE/ENDIF instr.Brian Paul
This is a little more logical. Suggested in bug report 25654.
2009-12-21r600: disallow negative offsets for relative addressing for nowAndre Maasikas
otherwise for example const[ADDR-3] gets us 253 - ALU_SRC_LITERAL which expects immediate floats to follow and hangs
2009-12-15r600: fix typos for vert-texAndre Maasikas
at least i think this is how it was meant to work
2009-12-15r600: add DDX DDY opcodesAndre Maasikas
2009-12-14r600 : add texture support for vertex shader.Richard Li
2009-12-09r600 : add pre-compile mesa shader calling interface, in order to handleRichard Li
complex built-in shader instructions.
2009-12-08r600: and finally fix SCSAndre Maasikas
2009-12-08r600: remove (now) dead codeAndre Maasikas
2009-12-08r600: fix SIN alsoAndre Maasikas
2009-12-08r600: use the new inline constants feature to fix COSAndre Maasikas
2009-12-08r600: add assembler support for literal(inline) constantsAndre Maasikas
and use it in cubemap instruction sequence for testing
2009-12-08r600: merge alu_instruction/alu_instruction2Andre Maasikas
2009-12-08r600: add ABS support for source regs to assemblerAndre Maasikas
use it in tex cube instruction sequence
2009-12-08r600: glsl - allow specifying texture sampler via uniformsAndre Maasikas
looks kinda hackish, should rethink later
2009-12-08r600: quick hack to get KIL_NV working - does condition TR only for nowAndre Maasikas
2009-12-08r600: wip glsl - refactor conditional instructions a bitAndre Maasikas
remember the dst register which is used for cond updates when it's time to use the cond codes issue a separate PRED instruction