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fd.o bug #25290
Suggested fix from Rafael Monica
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Let the hw decide (early vs late Z)
fixes fdo bug 25092
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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- consolidate DB render setup
- only enable perfect ZPASS counts and cull disable
when OQ is active
- enable early Z
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Conflicts:
src/mesa/drivers/dri/radeon/radeon_fbo.c
src/mesa/drivers/dri/s3v/s3v_tex.c
src/mesa/drivers/dri/s3v/s3v_xmesa.c
src/mesa/drivers/dri/trident/trident_context.c
src/mesa/main/debug.c
src/mesa/main/mipmap.c
src/mesa/main/texformat.c
src/mesa/main/texgetimage.c
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Based on initial patch from Stephan Schmid <stephan_2303@gmx.de>.
Basic idea is to dump the zpass count at the start and end of the query
and subtract to get the total number of visible fragments. HW writes
alternating qwords for up to 4 DBs. On the first pass, we start at
buffer address + 0; on the second pass, we start at buffer address + 8
(bytes). The resulting buffer at the end of the query looks like:
qw[0]: db0 start
qw[1]: db0 end
...
qw[6]: db3 start
qw[7]: db3 end
The MSB of each qword is the valid bit and the lower 63 bits are
the zpass count for that DB.
OQ on RV740 is disabled at the moment as it only seems to report
results for half of its DBs. This needs further investigation.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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fixes fdo bug 24248
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And remove other unneeded #includes while we're at it.
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makes blend functions work better
Signed-off-by: Dave Airlie <airlied@linux.ie>
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Signed-off-by: Dave Airlie <airlied@linux.ie>
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Radeon generic scissors code had problem that some of code was using exclusive
and some inclusive bottom right corner. Only r600 driver is using exclusive
coordinate so changed generic code to pass inclusive coordinate and r600 driver
changes BR coordinate to be exclusive.
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registers takes radius
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registers takes radius
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Setup the regs when we emit rather than during state setup.
In certain cases a proper CB target was never emitted.
This fixes bug 23658.
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fbos get angry when this happens.
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I forgot about r600 being here.
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Pulled from Dave's WIP patch.
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Should cover everything exported from the VS
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Gives a nice speed boost in most apps since
we only emit what state we need.
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switches more state handling to common code. We need
should be more fine grained with the state atoms
eventually.
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Slowing migrating to atom based system like
the other radeon drivers.
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- move shader-related state with the rest of the shader setup/emit
- start to track dirty state better
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fixes bug 23087
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- set MAX_LOD properly
- min texel pitch is 8 texels
- emit old command buffer when re-initing base state
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Set the flat shading bit on the appropriate PS input
depending on the type of attribute it is. The VS output
and PS input routing should probably be made more dynamic
at some point. We may want to use semantic ids to make
it easier.
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This breaks textures. We need to only set this bit for
attributes that that need flat shading.
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set VGT NUM_INSTANCES as part of the draw command rather
than as state as recommended by the pm4 guide. Also,
use the NUM_INSTANCES packet.
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