Age | Commit message (Collapse) | Author |
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R600_OUT_BATCH_RELOC doesn't really use offset so set it
in TEX_RESOURCE2
+ typo fix
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The ordering of texture components was
backwards for the floating point textures.
Signed-off-by: Pierre Ossman <pierre@ossman.eu>
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Use vertex program key mechanism and swizzle during vertex fetch - is there
a better way?
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Conflicts:
configure.ac
progs/demos/morph3d.c
progs/demos/textures.c
progs/glsl/shtest.c
progs/glsl/texaaline.c
progs/tests/packedpixels.c
progs/xdemos/corender.c
src/mesa/main/version.h
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these really shouldn't be exposed here
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these really shouldn't be exposed here
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fd.o bug #25290
Suggested fix from Rafael Monica
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fixes fdo bug 25679
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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makes testing other things easier - does not hang the card
TODO: enable TEX dependency tracking in vertex programs
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First time around render targets are not enabled yet (done in
r700SendRenderTargetState) so blend state is not emitted for any targets.
Affects first glClear in some mesa tests.
As a quick fix reorder state emit so that target is set first
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It's not implemented yet. fixes fdo bug 24047
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These are needed for HiZ which is not currently used and
the _BASE reg requires a reloc which is not currently supported
in the drm.
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otherwise
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Also avoids empty shader for "END" - seems to be somewhat valid fp
Maybe this can be done differently in the future (fake FRAG_RESULT_COLOR
already in Map_Fragment_Program() or is there a way to program the chip
to not hang in case of no exports.
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size was being calculated based on 3 bytes per pixel with 24 bit depth
instead of 4 bytes. This caused corruption in the bottom 25% of objects.
This finishes fixing the menu/text corruption in compiz/kde4.
Signed-off-by: Robert Noland <rnoland@2hip.net>
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Report unsupported attributes while I'm here.
Signed-off-by: Robert Noland <rnoland@2hip.net>
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Signed-off-by: Robert Noland <rnoland@2hip.net>
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Setting the wrong bo size resulting in an incomplete
read cache flush when reading the texture. This fixes the
compiz text corruption.
[agd5f: take hw pitch alignment into account]
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need this to properly test with piglit/glean vert/fragprog tests
copied mostly from r300, many thanks to osiris, nha, airlied, others...
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seems I overlooked this when removing hardcoded swizzles for this
one previously
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- KILLGT takes 2 arguments
- arb KIL has no dst register
- add TODO about clause ending but currently piglit fp-kil passes and
does not hang the card
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makes blend functions work better
Signed-off-by: Dave Airlie <airlied@linux.ie>
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Signed-off-by: Dave Airlie <airlied@linux.ie>
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Makes doom3 alot nicer..
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fixes fdo bug 24248
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Radeon generic scissors code had problem that some of code was using exclusive
and some inclusive bottom right corner. Only r600 driver is using exclusive
coordinate so changed generic code to pass inclusive coordinate and r600 driver
changes BR coordinate to be exclusive.
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seems to work here ...
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128 gprs, 256 reg-based consts
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- max texture size is 8k, but mesa doesn't support
that at the moment.
- attempt to set shader limits to what the hw actually
supports
- clean up some old r300 cruft
- no need to explicitly disable irqs. This is fixed
in the drm now.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
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- MUL_LIT is ALU.Trans instruction
- some Trans instructions can take 3 arguments
- don't clobber dst.x, use dst.z as temp, it'll get written correct
value in last insn
- respect source swizzles
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registers takes radius
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1D tile span support for depth/stencil/color/textures
Z and stencil buffers are always tiled, so this fixes
sw access to Z and stencil buffers. color and textures
are currently linear, but this adds span support when we
implement 1D tiling.
This fixes the text in progs/demos/engine and progs/tests/z*
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Noticed by rnoland on IRC.
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with some minor updates from Richard.
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noticed by taiu on IRC.
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We use t->bo for dri1 since r600 uses CS for dri1.
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if we have a BO here it means TFP and we should have set it
up already.
tested by b0le on #radeon
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Patch from taiu on IRC. fixes bug 23585
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